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@@ -138,6 +138,7 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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int nbits;
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u32 aper_low, aper_hi;
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u64 aper;
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+ u32 old_order;
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printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", num, slot, func);
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apsizereg = read_pci_config_16(num, slot, func, cap + 0x14);
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@@ -146,6 +147,9 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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return 0;
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}
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+ /* old_order could be the value from NB gart setting */
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+ old_order = *order;
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+
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apsize = apsizereg & 0xfff;
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/* Some BIOS use weird encodings not in the AGPv3 table. */
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if (apsize & 0xff)
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@@ -159,6 +163,16 @@ static __u32 __init read_agp(int num, int slot, int func, int cap, u32 *order)
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aper_hi = read_pci_config(num, slot, func, 0x14);
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aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
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+ /*
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+ * On some sick chips, APSIZE is 0. It means it wants 4G
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+ * so let double check that order, and lets trust AMD NB settings:
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+ */
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+ if (aper + (32UL<<(20 + *order)) > 0x100000000UL) {
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+ printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
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+ 32 << *order, apsizereg);
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+ *order = old_order;
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+ }
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+
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printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
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aper, 32 << *order, apsizereg);
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