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@@ -62,23 +62,8 @@ static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
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extern void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
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extern void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd);
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-static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
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-{
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- paravirt_alloc_pd(mm, __pa(pmd) >> PAGE_SHIFT);
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-
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- /* Note: almost everything apart from _PAGE_PRESENT is
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- reserved at the pmd (PDPT) level. */
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- set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
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+extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
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- /*
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- * According to Intel App note "TLBs, Paging-Structure Caches,
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- * and Their Invalidation", April 2007, document 317080-001,
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- * section 8.1: in PAE mode we explicitly have to flush the
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- * TLB via cr3 if the top-level pgd is changed...
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- */
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- if (mm == current->active_mm)
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- write_cr3(read_cr3());
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-}
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#endif /* CONFIG_X86_PAE */
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#endif /* CONFIG_X86_PAE */
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#endif /* _I386_PGALLOC_H */
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#endif /* _I386_PGALLOC_H */
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