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+/*
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+ * linux/drivers/gpio/pl061.c
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+ *
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+ * Copyright (C) 2008, 2009 Provigent Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
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+ *
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+ * Data sheet: ARM DDI 0190B, September 2000
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+ */
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+#include <linux/spinlock.h>
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+#include <linux/errno.h>
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+#include <linux/module.h>
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+#include <linux/list.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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+#include <linux/irq.h>
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+#include <linux/bitops.h>
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+#include <linux/workqueue.h>
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+#include <linux/gpio.h>
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+#include <linux/device.h>
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+#include <linux/amba/bus.h>
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+#include <linux/amba/pl061.h>
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+
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+#define GPIODIR 0x400
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+#define GPIOIS 0x404
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+#define GPIOIBE 0x408
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+#define GPIOIEV 0x40C
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+#define GPIOIE 0x410
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+#define GPIORIS 0x414
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+#define GPIOMIS 0x418
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+#define GPIOIC 0x41C
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+
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+#define PL061_GPIO_NR 8
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+
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+struct pl061_gpio {
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+ /* We use a list of pl061_gpio structs for each trigger IRQ in the main
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+ * interrupts controller of the system. We need this to support systems
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+ * in which more that one PL061s are connected to the same IRQ. The ISR
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+ * interates through this list to find the source of the interrupt.
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+ */
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+ struct list_head list;
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+
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+ /* Each of the two spinlocks protects a different set of hardware
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+ * regiters and data structurs. This decouples the code of the IRQ from
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+ * the GPIO code. This also makes the case of a GPIO routine call from
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+ * the IRQ code simpler.
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+ */
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+ spinlock_t lock; /* GPIO registers */
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+ spinlock_t irq_lock; /* IRQ registers */
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+
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+ void __iomem *base;
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+ unsigned irq_base;
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+ struct gpio_chip gc;
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+};
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+
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+static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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+{
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+ struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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+ unsigned long flags;
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+ unsigned char gpiodir;
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+
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+ if (offset >= gc->ngpio)
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+ return -EINVAL;
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+
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+ spin_lock_irqsave(&chip->lock, flags);
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+ gpiodir = readb(chip->base + GPIODIR);
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+ gpiodir &= ~(1 << offset);
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+ writeb(gpiodir, chip->base + GPIODIR);
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+ spin_unlock_irqrestore(&chip->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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+ int value)
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+{
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+ struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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+ unsigned long flags;
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+ unsigned char gpiodir;
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+
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+ if (offset >= gc->ngpio)
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+ return -EINVAL;
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+
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+ spin_lock_irqsave(&chip->lock, flags);
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+ writeb(!!value << offset, chip->base + (1 << (offset + 2)));
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+ gpiodir = readb(chip->base + GPIODIR);
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+ gpiodir |= 1 << offset;
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+ writeb(gpiodir, chip->base + GPIODIR);
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+ spin_unlock_irqrestore(&chip->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
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+{
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+ struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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+
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+ return !!readb(chip->base + (1 << (offset + 2)));
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+}
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+
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+static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
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+{
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+ struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
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+
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+ writeb(!!value << offset, chip->base + (1 << (offset + 2)));
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+}
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+
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+/*
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+ * PL061 GPIO IRQ
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+ */
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+static void pl061_irq_disable(unsigned irq)
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+{
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+ struct pl061_gpio *chip = get_irq_chip_data(irq);
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+ int offset = irq - chip->irq_base;
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+ unsigned long flags;
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+ u8 gpioie;
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+
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+ spin_lock_irqsave(&chip->irq_lock, flags);
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+ gpioie = readb(chip->base + GPIOIE);
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+ gpioie &= ~(1 << offset);
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+ writeb(gpioie, chip->base + GPIOIE);
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+ spin_unlock_irqrestore(&chip->irq_lock, flags);
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+}
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+
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+static void pl061_irq_enable(unsigned irq)
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+{
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+ struct pl061_gpio *chip = get_irq_chip_data(irq);
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+ int offset = irq - chip->irq_base;
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+ unsigned long flags;
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+ u8 gpioie;
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+
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+ spin_lock_irqsave(&chip->irq_lock, flags);
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+ gpioie = readb(chip->base + GPIOIE);
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+ gpioie |= 1 << offset;
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+ writeb(gpioie, chip->base + GPIOIE);
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+ spin_unlock_irqrestore(&chip->irq_lock, flags);
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+}
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+
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+static int pl061_irq_type(unsigned irq, unsigned trigger)
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+{
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+ struct pl061_gpio *chip = get_irq_chip_data(irq);
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+ int offset = irq - chip->irq_base;
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+ unsigned long flags;
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+ u8 gpiois, gpioibe, gpioiev;
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+
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+ if (offset < 0 || offset > PL061_GPIO_NR)
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+ return -EINVAL;
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+
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+ spin_lock_irqsave(&chip->irq_lock, flags);
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+
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+ gpioiev = readb(chip->base + GPIOIEV);
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+
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+ gpiois = readb(chip->base + GPIOIS);
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+ if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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+ gpiois |= 1 << offset;
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+ if (trigger & IRQ_TYPE_LEVEL_HIGH)
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+ gpioiev |= 1 << offset;
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+ else
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+ gpioiev &= ~(1 << offset);
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+ } else
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+ gpiois &= ~(1 << offset);
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+ writeb(gpiois, chip->base + GPIOIS);
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+
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+ gpioibe = readb(chip->base + GPIOIBE);
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+ if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
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+ gpioibe |= 1 << offset;
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+ else {
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+ gpioibe &= ~(1 << offset);
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+ if (trigger & IRQ_TYPE_EDGE_RISING)
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+ gpioiev |= 1 << offset;
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+ else
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+ gpioiev &= ~(1 << offset);
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+ }
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+ writeb(gpioibe, chip->base + GPIOIBE);
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+
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+ writeb(gpioiev, chip->base + GPIOIEV);
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+
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+ spin_unlock_irqrestore(&chip->irq_lock, flags);
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+
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+ return 0;
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+}
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+
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+static struct irq_chip pl061_irqchip = {
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+ .name = "GPIO",
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+ .enable = pl061_irq_enable,
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+ .disable = pl061_irq_disable,
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+ .set_type = pl061_irq_type,
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+};
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+
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+static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
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+{
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+ struct list_head *chip_list = get_irq_chip_data(irq);
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+ struct list_head *ptr;
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+ struct pl061_gpio *chip;
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+
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+ desc->chip->ack(irq);
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+ list_for_each(ptr, chip_list) {
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+ unsigned long pending;
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+ int gpio;
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+
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+ chip = list_entry(ptr, struct pl061_gpio, list);
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+ pending = readb(chip->base + GPIOMIS);
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+ writeb(pending, chip->base + GPIOIC);
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+
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+ if (pending == 0)
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+ continue;
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+
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+ for_each_bit(gpio, &pending, PL061_GPIO_NR)
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+ generic_handle_irq(gpio_to_irq(gpio));
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+ }
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+ desc->chip->unmask(irq);
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+}
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+
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+static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
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+{
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+ struct pl061_platform_data *pdata;
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+ struct pl061_gpio *chip;
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+ struct list_head *chip_list;
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+ int ret, irq, i;
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+ static unsigned long init_irq[BITS_TO_LONGS(NR_IRQS)];
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+
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+ pdata = dev->dev.platform_data;
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+ if (pdata == NULL)
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+ return -ENODEV;
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+
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+ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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+ if (chip == NULL)
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+ return -ENOMEM;
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+
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+ if (!request_mem_region(dev->res.start,
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+ resource_size(&dev->res), "pl061")) {
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+ ret = -EBUSY;
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+ goto free_mem;
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+ }
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+
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+ chip->base = ioremap(dev->res.start, resource_size(&dev->res));
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+ if (chip->base == NULL) {
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+ ret = -ENOMEM;
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+ goto release_region;
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+ }
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+
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+ spin_lock_init(&chip->lock);
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+ spin_lock_init(&chip->irq_lock);
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+ INIT_LIST_HEAD(&chip->list);
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+
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+ chip->gc.direction_input = pl061_direction_input;
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+ chip->gc.direction_output = pl061_direction_output;
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+ chip->gc.get = pl061_get_value;
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+ chip->gc.set = pl061_set_value;
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+ chip->gc.base = pdata->gpio_base;
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+ chip->gc.ngpio = PL061_GPIO_NR;
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+ chip->gc.label = dev_name(&dev->dev);
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+ chip->gc.dev = &dev->dev;
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+ chip->gc.owner = THIS_MODULE;
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+
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+ chip->irq_base = pdata->irq_base;
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+
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+ ret = gpiochip_add(&chip->gc);
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+ if (ret)
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+ goto iounmap;
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+
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+ /*
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+ * irq_chip support
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+ */
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+
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+ if (chip->irq_base == (unsigned) -1)
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+ return 0;
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+
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+ writeb(0, chip->base + GPIOIE); /* disable irqs */
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+ irq = dev->irq[0];
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+ if (irq < 0) {
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+ ret = -ENODEV;
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+ goto iounmap;
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+ }
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+ set_irq_chained_handler(irq, pl061_irq_handler);
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+ if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
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+ chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
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+ if (chip_list == NULL) {
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+ ret = -ENOMEM;
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+ goto iounmap;
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+ }
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+ INIT_LIST_HEAD(chip_list);
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+ set_irq_chip_data(irq, chip_list);
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+ } else
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+ chip_list = get_irq_chip_data(irq);
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+ list_add(&chip->list, chip_list);
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+
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+ for (i = 0; i < PL061_GPIO_NR; i++) {
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+ if (pdata->directions & (1 << i))
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+ pl061_direction_output(&chip->gc, i,
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+ pdata->values & (1 << i));
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+ else
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+ pl061_direction_input(&chip->gc, i);
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+
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+ set_irq_chip(i+chip->irq_base, &pl061_irqchip);
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+ set_irq_handler(i+chip->irq_base, handle_simple_irq);
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+ set_irq_flags(i+chip->irq_base, IRQF_VALID);
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+ set_irq_chip_data(i+chip->irq_base, chip);
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+ }
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+
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+ return 0;
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+
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+iounmap:
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+ iounmap(chip->base);
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+release_region:
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+ release_mem_region(dev->res.start, resource_size(&dev->res));
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+free_mem:
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+ kfree(chip);
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+
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+ return ret;
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+}
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+
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+static struct amba_id pl061_ids[] __initdata = {
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+ {
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+ .id = 0x00041061,
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+ .mask = 0x000fffff,
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+ },
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+ { 0, 0 },
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+};
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+
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+static struct amba_driver pl061_gpio_driver = {
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+ .drv = {
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+ .name = "pl061_gpio",
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+ },
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+ .id_table = pl061_ids,
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+ .probe = pl061_probe,
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+};
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+
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+static int __init pl061_gpio_init(void)
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+{
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+ return amba_driver_register(&pl061_gpio_driver);
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+}
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+subsys_initcall(pl061_gpio_init);
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+
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+MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
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+MODULE_DESCRIPTION("PL061 GPIO driver");
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+MODULE_LICENSE("GPL");
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