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@@ -42,6 +42,7 @@
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#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
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#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
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#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
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+#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
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#define MV78XX0_CORE_REGS_SIZE SZ_16K
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#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
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@@ -59,6 +60,7 @@
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* Core-specific peripheral registers.
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*/
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#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
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+#define BRIDGE_PHYS_BASE (MV78XX0_CORE_REGS_PHYS_BASE)
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/*
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* Register Map
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