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@@ -0,0 +1,102 @@
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+/*
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+ * SGI NMI support routines
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ *
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+ * Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved.
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+ * Copyright (c) Mike Travis
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+ */
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+
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+#include <linux/cpu.h>
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+#include <linux/nmi.h>
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+
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+#include <asm/apic.h>
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+#include <asm/nmi.h>
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+#include <asm/uv/uv.h>
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+#include <asm/uv/uv_hub.h>
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+#include <asm/uv/uv_mmrs.h>
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+
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+/* BMC sets a bit this MMR non-zero before sending an NMI */
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+#define UVH_NMI_MMR UVH_SCRATCH5
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+#define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8)
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+#define UV_NMI_PENDING_MASK (1UL << 63)
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+DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
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+static DEFINE_SPINLOCK(uv_nmi_lock);
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+
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+/*
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+ * When NMI is received, print a stack trace.
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+ */
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+int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
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+{
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+ unsigned long real_uv_nmi;
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+ int bid;
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+
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+ /*
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+ * Each blade has an MMR that indicates when an NMI has been sent
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+ * to cpus on the blade. If an NMI is detected, atomically
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+ * clear the MMR and update a per-blade NMI count used to
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+ * cause each cpu on the blade to notice a new NMI.
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+ */
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+ bid = uv_numa_blade_id();
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+ real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
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+
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+ if (unlikely(real_uv_nmi)) {
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+ spin_lock(&uv_blade_info[bid].nmi_lock);
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+ real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) &
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+ UV_NMI_PENDING_MASK);
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+ if (real_uv_nmi) {
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+ uv_blade_info[bid].nmi_count++;
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+ uv_write_local_mmr(UVH_NMI_MMR_CLEAR,
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+ UV_NMI_PENDING_MASK);
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+ }
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+ spin_unlock(&uv_blade_info[bid].nmi_lock);
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+ }
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+
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+ if (likely(__get_cpu_var(cpu_last_nmi_count) ==
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+ uv_blade_info[bid].nmi_count))
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+ return NMI_DONE;
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+
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+ __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
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+
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+ /*
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+ * Use a lock so only one cpu prints at a time.
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+ * This prevents intermixed output.
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+ */
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+ spin_lock(&uv_nmi_lock);
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+ pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
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+ dump_stack();
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+ spin_unlock(&uv_nmi_lock);
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+
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+ return NMI_HANDLED;
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+}
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+
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+void uv_register_nmi_notifier(void)
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+{
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+ if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv"))
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+ pr_warn("UV NMI handler failed to register\n");
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+}
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+
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+void uv_nmi_init(void)
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+{
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+ unsigned int value;
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+
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+ /*
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+ * Unmask NMI on all cpus
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+ */
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+ value = apic_read(APIC_LVT1) | APIC_DM_NMI;
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+ value &= ~APIC_LVT_MASKED;
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+ apic_write(APIC_LVT1, value);
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+}
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+
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Mike Travis