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+/*
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+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/cpufreq.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/opp.h>
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+#include <linux/platform_device.h>
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+#include <linux/regulator/consumer.h>
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+
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+#define PU_SOC_VOLTAGE_NORMAL 1250000
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+#define PU_SOC_VOLTAGE_HIGH 1275000
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+#define FREQ_1P2_GHZ 1200000000
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+
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+static struct regulator *arm_reg;
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+static struct regulator *pu_reg;
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+static struct regulator *soc_reg;
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+
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+static struct clk *arm_clk;
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+static struct clk *pll1_sys_clk;
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+static struct clk *pll1_sw_clk;
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+static struct clk *step_clk;
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+static struct clk *pll2_pfd2_396m_clk;
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+
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+static struct device *cpu_dev;
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+static struct cpufreq_frequency_table *freq_table;
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+static unsigned int transition_latency;
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+
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+static int imx6q_verify_speed(struct cpufreq_policy *policy)
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+{
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+ return cpufreq_frequency_table_verify(policy, freq_table);
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+}
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+
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+static unsigned int imx6q_get_speed(unsigned int cpu)
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+{
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+ return clk_get_rate(arm_clk) / 1000;
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+}
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+
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+static int imx6q_set_target(struct cpufreq_policy *policy,
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+ unsigned int target_freq, unsigned int relation)
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+{
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+ struct cpufreq_freqs freqs;
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+ struct opp *opp;
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+ unsigned long freq_hz, volt, volt_old;
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+ unsigned int index, cpu;
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+ int ret;
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+
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+ ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
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+ relation, &index);
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+ if (ret) {
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+ dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
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+ target_freq, ret);
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+ return ret;
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+ }
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+
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+ freqs.new = freq_table[index].frequency;
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+ freq_hz = freqs.new * 1000;
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+ freqs.old = clk_get_rate(arm_clk) / 1000;
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+
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+ if (freqs.old == freqs.new)
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+ return 0;
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+
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+ for_each_online_cpu(cpu) {
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+ freqs.cpu = cpu;
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+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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+ }
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+
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+ rcu_read_lock();
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+ opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
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+ if (IS_ERR(opp)) {
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+ rcu_read_unlock();
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+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
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+ return PTR_ERR(opp);
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+ }
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+
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+ volt = opp_get_voltage(opp);
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+ rcu_read_unlock();
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+ volt_old = regulator_get_voltage(arm_reg);
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+
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+ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
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+ freqs.old / 1000, volt_old / 1000,
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+ freqs.new / 1000, volt / 1000);
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+
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+ /* scaling up? scale voltage before frequency */
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+ if (freqs.new > freqs.old) {
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+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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+ if (ret) {
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+ dev_err(cpu_dev,
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+ "failed to scale vddarm up: %d\n", ret);
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+ return ret;
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+ }
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+
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+ /*
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+ * Need to increase vddpu and vddsoc for safety
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+ * if we are about to run at 1.2 GHz.
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+ */
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+ if (freqs.new == FREQ_1P2_GHZ / 1000) {
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+ regulator_set_voltage_tol(pu_reg,
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+ PU_SOC_VOLTAGE_HIGH, 0);
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+ regulator_set_voltage_tol(soc_reg,
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+ PU_SOC_VOLTAGE_HIGH, 0);
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+ }
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+ }
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+
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+ /*
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+ * The setpoints are selected per PLL/PDF frequencies, so we need to
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+ * reprogram PLL for frequency scaling. The procedure of reprogramming
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+ * PLL1 is as below.
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+ *
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+ * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
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+ * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
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+ * - Disable pll2_pfd2_396m_clk
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+ */
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+ clk_prepare_enable(pll2_pfd2_396m_clk);
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+ clk_set_parent(step_clk, pll2_pfd2_396m_clk);
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+ clk_set_parent(pll1_sw_clk, step_clk);
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+ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
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+ clk_set_rate(pll1_sys_clk, freqs.new * 1000);
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+ /*
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+ * If we are leaving 396 MHz set-point, we need to enable
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+ * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
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+ * their use count correct.
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+ */
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+ if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
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+ clk_prepare_enable(pll1_sys_clk);
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+ clk_disable_unprepare(pll2_pfd2_396m_clk);
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+ }
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+ clk_set_parent(pll1_sw_clk, pll1_sys_clk);
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+ clk_disable_unprepare(pll2_pfd2_396m_clk);
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+ } else {
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+ /*
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+ * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
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+ * to provide the frequency.
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+ */
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+ clk_disable_unprepare(pll1_sys_clk);
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+ }
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+
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+ /* Ensure the arm clock divider is what we expect */
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+ ret = clk_set_rate(arm_clk, freqs.new * 1000);
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+ if (ret) {
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+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
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+ regulator_set_voltage_tol(arm_reg, volt_old, 0);
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+ return ret;
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+ }
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+
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+ /* scaling down? scale voltage after frequency */
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+ if (freqs.new < freqs.old) {
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+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
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+ if (ret)
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+ dev_warn(cpu_dev,
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+ "failed to scale vddarm down: %d\n", ret);
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+
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+ if (freqs.old == FREQ_1P2_GHZ / 1000) {
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+ regulator_set_voltage_tol(pu_reg,
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+ PU_SOC_VOLTAGE_NORMAL, 0);
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+ regulator_set_voltage_tol(soc_reg,
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+ PU_SOC_VOLTAGE_NORMAL, 0);
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+ }
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+ }
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+
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+ for_each_online_cpu(cpu) {
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+ freqs.cpu = cpu;
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+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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+ }
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+
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+ return 0;
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+}
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+
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+static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
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+{
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+ int ret;
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+
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+ ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
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+ if (ret) {
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+ dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
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+ return ret;
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+ }
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+
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+ policy->cpuinfo.transition_latency = transition_latency;
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+ policy->cur = clk_get_rate(arm_clk) / 1000;
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+ cpumask_setall(policy->cpus);
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+ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
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+
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+ return 0;
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+}
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+
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+static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
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+{
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+ cpufreq_frequency_table_put_attr(policy->cpu);
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+ return 0;
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+}
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+
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+static struct freq_attr *imx6q_cpufreq_attr[] = {
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+ &cpufreq_freq_attr_scaling_available_freqs,
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+ NULL,
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+};
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+
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+static struct cpufreq_driver imx6q_cpufreq_driver = {
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+ .verify = imx6q_verify_speed,
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+ .target = imx6q_set_target,
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+ .get = imx6q_get_speed,
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+ .init = imx6q_cpufreq_init,
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+ .exit = imx6q_cpufreq_exit,
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+ .name = "imx6q-cpufreq",
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+ .attr = imx6q_cpufreq_attr,
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+};
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+
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+static int imx6q_cpufreq_probe(struct platform_device *pdev)
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+{
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+ struct device_node *np;
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+ struct opp *opp;
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+ unsigned long min_volt, max_volt;
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+ int num, ret;
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+
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+ cpu_dev = &pdev->dev;
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+
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+ np = of_find_node_by_path("/cpus/cpu@0");
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+ if (!np) {
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+ dev_err(cpu_dev, "failed to find cpu0 node\n");
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+ return -ENOENT;
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+ }
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+
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+ cpu_dev->of_node = np;
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+
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+ arm_clk = devm_clk_get(cpu_dev, "arm");
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+ pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
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+ pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
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+ step_clk = devm_clk_get(cpu_dev, "step");
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+ pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
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+ if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
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+ IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
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+ dev_err(cpu_dev, "failed to get clocks\n");
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+ ret = -ENOENT;
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+ goto put_node;
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+ }
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+
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+ arm_reg = devm_regulator_get(cpu_dev, "arm");
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+ pu_reg = devm_regulator_get(cpu_dev, "pu");
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+ soc_reg = devm_regulator_get(cpu_dev, "soc");
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+ if (!arm_reg || !pu_reg || !soc_reg) {
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+ dev_err(cpu_dev, "failed to get regulators\n");
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+ ret = -ENOENT;
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+ goto put_node;
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+ }
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+
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+ /* We expect an OPP table supplied by platform */
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+ num = opp_get_opp_count(cpu_dev);
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+ if (num < 0) {
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+ ret = num;
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+ dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
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+ goto put_node;
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+ }
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+
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+ ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
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+ if (ret) {
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+ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
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+ goto put_node;
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+ }
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+
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+ if (of_property_read_u32(np, "clock-latency", &transition_latency))
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+ transition_latency = CPUFREQ_ETERNAL;
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+
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+ /*
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+ * OPP is maintained in order of increasing frequency, and
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+ * freq_table initialised from OPP is therefore sorted in the
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+ * same order.
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+ */
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+ rcu_read_lock();
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+ opp = opp_find_freq_exact(cpu_dev,
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+ freq_table[0].frequency * 1000, true);
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+ min_volt = opp_get_voltage(opp);
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+ opp = opp_find_freq_exact(cpu_dev,
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+ freq_table[--num].frequency * 1000, true);
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+ max_volt = opp_get_voltage(opp);
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+ rcu_read_unlock();
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+ ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
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+ if (ret > 0)
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+ transition_latency += ret * 1000;
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+
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+ /* Count vddpu and vddsoc latency in for 1.2 GHz support */
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+ if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
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+ ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
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+ PU_SOC_VOLTAGE_HIGH);
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+ if (ret > 0)
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+ transition_latency += ret * 1000;
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+ ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
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+ PU_SOC_VOLTAGE_HIGH);
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+ if (ret > 0)
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+ transition_latency += ret * 1000;
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+ }
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+
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+ ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
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+ if (ret) {
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+ dev_err(cpu_dev, "failed register driver: %d\n", ret);
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+ goto free_freq_table;
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+ }
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+
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+ of_node_put(np);
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+ return 0;
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+
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+free_freq_table:
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+ opp_free_cpufreq_table(cpu_dev, &freq_table);
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+put_node:
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+ of_node_put(np);
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+ return ret;
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+}
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+
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+static int imx6q_cpufreq_remove(struct platform_device *pdev)
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+{
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+ cpufreq_unregister_driver(&imx6q_cpufreq_driver);
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+ opp_free_cpufreq_table(cpu_dev, &freq_table);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver imx6q_cpufreq_platdrv = {
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+ .driver = {
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+ .name = "imx6q-cpufreq",
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+ .owner = THIS_MODULE,
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+ },
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+ .probe = imx6q_cpufreq_probe,
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+ .remove = imx6q_cpufreq_remove,
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+};
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+module_platform_driver(imx6q_cpufreq_platdrv);
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+
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+MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
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+MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
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+MODULE_LICENSE("GPL");
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