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@@ -403,7 +403,6 @@ void __init prom_init(void)
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const int coreid = cvmx_get_core_num();
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int i;
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int argc;
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- struct uart_port octeon_port;
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#ifdef CONFIG_CAVIUM_RESERVE32
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int64_t addr = -1;
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#endif
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@@ -610,30 +609,6 @@ void __init prom_init(void)
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_machine_restart = octeon_restart;
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_machine_halt = octeon_halt;
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- memset(&octeon_port, 0, sizeof(octeon_port));
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- /*
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- * For early_serial_setup we don't set the port type or
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- * UPF_FIXED_TYPE.
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- */
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- octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ;
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- octeon_port.iotype = UPIO_MEM;
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- /* I/O addresses are every 8 bytes */
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- octeon_port.regshift = 3;
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- /* Clock rate of the chip */
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- octeon_port.uartclk = mips_hpt_frequency;
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- octeon_port.fifosize = 64;
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- octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart);
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- octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase);
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- octeon_port.serial_in = octeon_serial_in;
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- octeon_port.serial_out = octeon_serial_out;
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-#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
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- octeon_port.line = 0;
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-#else
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- octeon_port.line = octeon_uart;
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-#endif
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- octeon_port.irq = 42 + octeon_uart;
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- early_serial_setup(&octeon_port);
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-
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octeon_user_io_init();
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register_smp_ops(&octeon_smp_ops);
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}
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