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@@ -52,7 +52,7 @@
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#include "sky2.h"
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#define DRV_NAME "sky2"
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-#define DRV_VERSION "1.19"
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+#define DRV_VERSION "1.20"
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#define PFX DRV_NAME " "
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/*
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@@ -121,6 +121,7 @@ static const struct pci_device_id sky2_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
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+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
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@@ -134,6 +135,7 @@ static const struct pci_device_id sky2_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
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{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
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+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
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{ 0 }
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};
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@@ -156,7 +158,7 @@ static const char *yukon2_name[] = {
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static void sky2_set_multicast(struct net_device *dev);
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-/* Access to external PHY */
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+/* Access to PHY via serial interconnect */
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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
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{
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int i;
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@@ -166,13 +168,22 @@ static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
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GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
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for (i = 0; i < PHY_RETRIES; i++) {
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- if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
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+ u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
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+ if (ctrl == 0xffff)
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+ goto io_error;
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+
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+ if (!(ctrl & GM_SMI_CT_BUSY))
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return 0;
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- udelay(1);
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+
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+ udelay(10);
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}
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- printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
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+ dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
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return -ETIMEDOUT;
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+
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+io_error:
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+ dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
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+ return -EIO;
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}
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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
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@@ -183,23 +194,29 @@ static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
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| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
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for (i = 0; i < PHY_RETRIES; i++) {
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- if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
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+ u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
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+ if (ctrl == 0xffff)
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+ goto io_error;
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+
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+ if (ctrl & GM_SMI_CT_RD_VAL) {
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*val = gma_read16(hw, port, GM_SMI_DATA);
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return 0;
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}
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- udelay(1);
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+ udelay(10);
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}
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+ dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
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return -ETIMEDOUT;
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+io_error:
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+ dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
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+ return -EIO;
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}
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-static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
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+static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
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{
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u16 v;
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-
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- if (__gm_phy_read(hw, port, reg, &v) != 0)
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- printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
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+ __gm_phy_read(hw, port, reg, &v);
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return v;
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}
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@@ -273,8 +290,6 @@ static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
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/* disable all GMAC IRQ's */
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sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
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- /* disable PHY IRQs */
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- gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
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gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
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gma_write16(hw, port, GM_MC_ADDR_H2, 0);
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@@ -1805,29 +1820,6 @@ static void sky2_link_up(struct sky2_port *sky2)
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sky2_write8(hw, SK_REG(port, LNK_LED_REG),
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LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
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- if (hw->flags & SKY2_HW_NEWER_PHY) {
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- u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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- u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
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-
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- switch(sky2->speed) {
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- case SPEED_10:
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- led |= PHY_M_LEDC_INIT_CTRL(7);
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- break;
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-
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- case SPEED_100:
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- led |= PHY_M_LEDC_STA1_CTRL(7);
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- break;
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-
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- case SPEED_1000:
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- led |= PHY_M_LEDC_STA0_CTRL(7);
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- break;
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- }
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-
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- gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
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- gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
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- gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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- }
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-
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if (netif_msg_link(sky2))
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printk(KERN_INFO PFX
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"%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
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@@ -2247,20 +2239,26 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
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do {
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struct sky2_port *sky2;
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struct sky2_status_le *le = hw->st_le + hw->st_idx;
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- unsigned port = le->css & CSS_LINK_BIT;
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+ unsigned port;
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struct net_device *dev;
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struct sk_buff *skb;
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u32 status;
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u16 length;
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+ u8 opcode = le->opcode;
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+
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+ if (!(opcode & HW_OWNER))
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+ break;
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hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
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+ port = le->css & CSS_LINK_BIT;
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dev = hw->dev[port];
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sky2 = netdev_priv(dev);
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length = le16_to_cpu(le->length);
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status = le32_to_cpu(le->status);
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- switch (le->opcode & ~HW_OWNER) {
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+ le->opcode = 0;
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+ switch (opcode & ~HW_OWNER) {
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case OP_RXSTAT:
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++rx[port];
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skb = sky2_receive(dev, length, status);
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@@ -2353,7 +2351,7 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
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default:
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if (net_ratelimit())
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printk(KERN_WARNING PFX
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- "unknown status opcode 0x%x\n", le->opcode);
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+ "unknown status opcode 0x%x\n", opcode);
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}
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} while (hw->st_idx != idx);
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@@ -2439,13 +2437,26 @@ static void sky2_hw_intr(struct sky2_hw *hw)
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if (status & Y2_IS_PCI_EXP) {
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/* PCI-Express uncorrectable Error occurred */
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- int pos = pci_find_aer_capability(hw->pdev);
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+ int aer = pci_find_aer_capability(hw->pdev);
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u32 err;
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- pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_STATUS, &err);
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+ if (aer) {
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+ pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS,
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+ &err);
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+ pci_cleanup_aer_uncorrect_error_status(pdev);
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+ } else {
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+ /* Either AER not configured, or not working
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+ * because of bad MMCONFIG, so just do recover
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+ * manually.
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+ */
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+ err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
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+ sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
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+ 0xfffffffful);
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+ }
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+
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if (net_ratelimit())
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dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
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- pci_cleanup_aer_uncorrect_error_status(pdev);
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+
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}
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if (status & Y2_HWE_L1_MASK)
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@@ -2791,6 +2802,9 @@ static void sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, B0_CTST, CS_RST_SET);
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sky2_write8(hw, B0_CTST, CS_RST_CLR);
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+ /* allow writes to PCI config */
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+ sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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+
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/* clear PCI errors, if any */
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pci_read_config_word(pdev, PCI_STATUS, &status);
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status |= PCI_STATUS_ERROR_BITS;
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@@ -2800,9 +2814,18 @@ static void sky2_reset(struct sky2_hw *hw)
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cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (cap) {
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- /* Check for advanced error reporting */
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- pci_cleanup_aer_uncorrect_error_status(pdev);
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- pci_cleanup_aer_correct_error_status(pdev);
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+ if (pci_find_aer_capability(pdev)) {
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+ /* Check for advanced error reporting */
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+ pci_cleanup_aer_uncorrect_error_status(pdev);
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+ pci_cleanup_aer_correct_error_status(pdev);
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+ } else {
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+ dev_warn(&pdev->dev,
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+ "PCI Express Advanced Error Reporting"
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+ " not configured or MMCONFIG problem?\n");
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+
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+ sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
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+ 0xfffffffful);
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+ }
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/* If error bit is stuck on ignore it */
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if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
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@@ -3974,7 +3997,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
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dev->tx_timeout = sky2_tx_timeout;
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dev->watchdog_timeo = TX_WATCHDOG;
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#ifdef CONFIG_NET_POLL_CONTROLLER
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- dev->poll_controller = sky2_netpoll;
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+ if (port == 0)
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+ dev->poll_controller = sky2_netpoll;
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#endif
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sky2 = netdev_priv(dev);
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