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@@ -120,7 +120,8 @@
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#define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
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#define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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-#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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+#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
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+#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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@@ -591,6 +592,9 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
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return 0;
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return 0;
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}
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}
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+/* half the RX buffer size */
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+#define CTSTL 16
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+
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static int imx_startup(struct uart_port *port)
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static int imx_startup(struct uart_port *port)
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{
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{
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struct imx_port *sport = (struct imx_port *)port;
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struct imx_port *sport = (struct imx_port *)port;
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@@ -607,6 +611,10 @@ static int imx_startup(struct uart_port *port)
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if (USE_IRDA(sport))
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if (USE_IRDA(sport))
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temp |= UCR4_IRSC;
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temp |= UCR4_IRSC;
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+ /* set the trigger level for CTS */
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+ temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
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+ temp |= CTSTL<< UCR4_CTSTL_SHF;
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+
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writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
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writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
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if (USE_IRDA(sport)) {
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if (USE_IRDA(sport)) {
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