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@@ -45,9 +45,6 @@
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#define OMAP2_MCSPI_MAX_FREQ 48000000
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-/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
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-#define OMAP2_MCSPI_MAX_CTRL 4
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-
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#define OMAP2_MCSPI_REVISION 0x00
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#define OMAP2_MCSPI_SYSSTATUS 0x14
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#define OMAP2_MCSPI_IRQSTATUS 0x18
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@@ -111,6 +108,16 @@ struct omap2_mcspi_dma {
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#define DMA_MIN_BYTES 160
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+/*
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+ * Used for context save and restore, structure members to be updated whenever
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+ * corresponding registers are modified.
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+ */
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+struct omap2_mcspi_regs {
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+ u32 modulctrl;
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+ u32 wakeupenable;
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+ struct list_head cs;
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+};
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+
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struct omap2_mcspi {
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struct work_struct work;
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/* lock protects queue and registers */
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@@ -122,8 +129,9 @@ struct omap2_mcspi {
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unsigned long phys;
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/* SPI1 has 4 channels, while SPI2 has 2 */
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struct omap2_mcspi_dma *dma_channels;
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- struct device *dev;
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+ struct device *dev;
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struct workqueue_struct *wq;
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+ struct omap2_mcspi_regs ctx;
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};
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struct omap2_mcspi_cs {
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@@ -135,17 +143,6 @@ struct omap2_mcspi_cs {
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u32 chconf0;
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};
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-/* used for context save and restore, structure members to be updated whenever
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- * corresponding registers are modified.
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- */
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-struct omap2_mcspi_regs {
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- u32 modulctrl;
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- u32 wakeupenable;
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- struct list_head cs;
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-};
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-
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-static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
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-
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#define MOD_REG_BIT(val, mask, set) do { \
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if (set) \
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val |= mask; \
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@@ -236,9 +233,12 @@ static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
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static void omap2_mcspi_set_master_mode(struct spi_master *master)
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{
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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u32 l;
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- /* setup when switching from (reset default) slave mode
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+ /*
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+ * Setup when switching from (reset default) slave mode
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* to single-channel master mode
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*/
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l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
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@@ -247,24 +247,20 @@ static void omap2_mcspi_set_master_mode(struct spi_master *master)
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MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
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mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
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- omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
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+ ctx->modulctrl = l;
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}
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static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
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{
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- struct spi_master *spi_cntrl;
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- struct omap2_mcspi_cs *cs;
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- spi_cntrl = mcspi->master;
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+ struct spi_master *spi_cntrl = mcspi->master;
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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+ struct omap2_mcspi_cs *cs;
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/* McSPI: context restore */
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- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
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- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
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+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
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+ mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
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- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
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- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
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-
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- list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
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- node)
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+ list_for_each_entry(cs, &ctx->cs, node)
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__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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}
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static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
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@@ -777,7 +773,8 @@ static int omap2_mcspi_request_dma(struct spi_device *spi)
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static int omap2_mcspi_setup(struct spi_device *spi)
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{
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int ret;
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- struct omap2_mcspi *mcspi;
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+ struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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struct omap2_mcspi_dma *mcspi_dma;
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struct omap2_mcspi_cs *cs = spi->controller_state;
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@@ -787,7 +784,6 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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return -EINVAL;
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}
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- mcspi = spi_master_get_devdata(spi->master);
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mcspi_dma = &mcspi->dma_channels[spi->chip_select];
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if (!cs) {
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@@ -799,8 +795,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
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cs->chconf0 = 0;
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spi->controller_state = cs;
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/* Link this to context save list */
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- list_add_tail(&cs->node,
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- &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
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+ list_add_tail(&cs->node, &ctx->cs);
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}
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if (mcspi_dma->dma_rx_channel == -1
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@@ -1052,8 +1047,9 @@ static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
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static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
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{
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struct spi_master *master = mcspi->master;
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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u32 tmp;
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- int ret = 0;
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+ int ret = 0;
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ret = omap2_mcspi_enable_clocks(mcspi);
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if (ret < 0)
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@@ -1061,7 +1057,7 @@ static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
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tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
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mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
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- omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
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+ ctx->wakeupenable = tmp;
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omap2_mcspi_set_master_mode(master);
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omap2_mcspi_disable_clocks(mcspi);
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@@ -1108,7 +1104,6 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
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struct omap2_mcspi *mcspi;
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struct resource *r;
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int status = 0, i;
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- char wq_name[20];
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u32 regs_offset = 0;
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static int bus_num = 1;
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struct device_node *node = pdev->dev.of_node;
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@@ -1149,8 +1144,7 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
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mcspi = spi_master_get_devdata(master);
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mcspi->master = master;
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- sprintf(wq_name, "omap2_mcspi/%d", master->bus_num);
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- mcspi->wq = alloc_workqueue(wq_name, WQ_MEM_RECLAIM, 1);
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+ mcspi->wq = alloc_workqueue(dev_name(&pdev->dev), WQ_MEM_RECLAIM, 1);
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if (mcspi->wq == NULL) {
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status = -ENOMEM;
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goto free_master;
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@@ -1178,7 +1172,7 @@ static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
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spin_lock_init(&mcspi->lock);
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INIT_LIST_HEAD(&mcspi->msg_queue);
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- INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
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+ INIT_LIST_HEAD(&mcspi->ctx.cs);
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mcspi->dma_channels = kcalloc(master->num_chipselect,
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sizeof(struct omap2_mcspi_dma),
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@@ -1275,13 +1269,12 @@ static int omap2_mcspi_resume(struct device *dev)
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{
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struct spi_master *master = dev_get_drvdata(dev);
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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- struct omap2_mcspi_cs *cs;
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+ struct omap2_mcspi_regs *ctx = &mcspi->ctx;
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+ struct omap2_mcspi_cs *cs;
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omap2_mcspi_enable_clocks(mcspi);
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- list_for_each_entry(cs, &omap2_mcspi_ctx[master->bus_num - 1].cs,
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- node) {
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+ list_for_each_entry(cs, &ctx->cs, node) {
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if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
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-
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/*
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* We need to toggle CS state for OMAP take this
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* change in account.
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