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@@ -196,22 +196,21 @@ enum ath_ini_subsys {
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enum ath9k_hw_caps {
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ATH9K_HW_CAP_HT = BIT(0),
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ATH9K_HW_CAP_RFSILENT = BIT(1),
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- ATH9K_HW_CAP_CST = BIT(2),
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- ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
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- ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
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- ATH9K_HW_CAP_EDMA = BIT(6),
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- ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
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- ATH9K_HW_CAP_LDPC = BIT(8),
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- ATH9K_HW_CAP_FASTCLOCK = BIT(9),
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- ATH9K_HW_CAP_SGI_20 = BIT(10),
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- ATH9K_HW_CAP_PAPRD = BIT(11),
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- ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
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- ATH9K_HW_CAP_2GHZ = BIT(13),
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- ATH9K_HW_CAP_5GHZ = BIT(14),
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- ATH9K_HW_CAP_APM = BIT(15),
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- ATH9K_HW_CAP_RTT = BIT(16),
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- ATH9K_HW_CAP_MCI = BIT(17),
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- ATH9K_HW_CAP_DFS = BIT(18),
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+ ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
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+ ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
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+ ATH9K_HW_CAP_EDMA = BIT(4),
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+ ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
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+ ATH9K_HW_CAP_LDPC = BIT(6),
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+ ATH9K_HW_CAP_FASTCLOCK = BIT(7),
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+ ATH9K_HW_CAP_SGI_20 = BIT(8),
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+ ATH9K_HW_CAP_PAPRD = BIT(9),
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+ ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
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+ ATH9K_HW_CAP_2GHZ = BIT(11),
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+ ATH9K_HW_CAP_5GHZ = BIT(12),
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+ ATH9K_HW_CAP_APM = BIT(13),
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+ ATH9K_HW_CAP_RTT = BIT(14),
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+ ATH9K_HW_CAP_MCI = BIT(15),
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+ ATH9K_HW_CAP_DFS = BIT(16),
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};
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struct ath9k_hw_capabilities {
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