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@@ -9,7 +9,7 @@
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** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
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** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
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**
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**
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** Web site: www.areca.com.tw
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** Web site: www.areca.com.tw
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-** E-mail: erich@areca.com.tw
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+** E-mail: support@areca.com.tw
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**
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**
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** This program is free software; you can redistribute it and/or modify
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License version 2 as
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** it under the terms of the GNU General Public License version 2 as
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@@ -45,19 +45,26 @@
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#include <linux/interrupt.h>
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#include <linux/interrupt.h>
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struct class_device_attribute;
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struct class_device_attribute;
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-
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-#define ARCMSR_MAX_OUTSTANDING_CMD 256
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-#define ARCMSR_MAX_FREECCB_NUM 288
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-#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.14"
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+/*The limit of outstanding scsi command that firmware can handle*/
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+#define ARCMSR_MAX_OUTSTANDING_CMD 256
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+#define ARCMSR_MAX_FREECCB_NUM 320
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+#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2007/08/30"
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_SCSI_INITIATOR_ID 255
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#define ARCMSR_MAX_XFER_SECTORS 512
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#define ARCMSR_MAX_XFER_SECTORS 512
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-#define ARCMSR_MAX_XFER_SECTORS_B 4096
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-#define ARCMSR_MAX_TARGETID 17
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-#define ARCMSR_MAX_TARGETLUN 8
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-#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
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-#define ARCMSR_MAX_QBUFFER 4096
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-#define ARCMSR_MAX_SG_ENTRIES 38
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-
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+#define ARCMSR_MAX_XFER_SECTORS_B 4096
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+#define ARCMSR_MAX_TARGETID 17
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+#define ARCMSR_MAX_TARGETLUN 8
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+#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
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+#define ARCMSR_MAX_QBUFFER 4096
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+#define ARCMSR_MAX_SG_ENTRIES 38
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+#define ARCMSR_MAX_HBB_POSTQUEUE 264
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+/*
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+**********************************************************************************
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+**
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+**********************************************************************************
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+*/
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+#define ARC_SUCCESS 0
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+#define ARC_FAILURE 1
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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** split 64bits dma addressing
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** split 64bits dma addressing
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@@ -90,7 +97,7 @@ struct CMD_MESSAGE_FIELD
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uint8_t messagedatabuffer[1032];
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uint8_t messagedatabuffer[1032];
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};
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};
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/* IOP message transfer */
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/* IOP message transfer */
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-#define ARCMSR_MESSAGE_FAIL 0x0001
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+#define ARCMSR_MESSAGE_FAIL 0x0001
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/* DeviceType */
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/* DeviceType */
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#define ARECA_SATA_RAID 0x90000000
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#define ARECA_SATA_RAID 0x90000000
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/* FunctionCode */
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/* FunctionCode */
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@@ -163,27 +170,27 @@ struct QBUFFER
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};
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};
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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-** FIRMWARE INFO
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+** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
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*******************************************************************************
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*******************************************************************************
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*/
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*/
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struct FIRMWARE_INFO
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struct FIRMWARE_INFO
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{
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{
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- uint32_t signature; /*0, 00-03*/
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- uint32_t request_len; /*1, 04-07*/
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- uint32_t numbers_queue; /*2, 08-11*/
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+ uint32_t signature; /*0, 00-03*/
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+ uint32_t request_len; /*1, 04-07*/
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+ uint32_t numbers_queue; /*2, 08-11*/
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uint32_t sdram_size; /*3, 12-15*/
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uint32_t sdram_size; /*3, 12-15*/
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- uint32_t ide_channels; /*4, 16-19*/
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- char vendor[40]; /*5, 20-59*/
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- char model[8]; /*15, 60-67*/
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- char firmware_ver[16]; /*17, 68-83*/
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- char device_map[16]; /*21, 84-99*/
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+ uint32_t ide_channels; /*4, 16-19*/
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+ char vendor[40]; /*5, 20-59*/
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+ char model[8]; /*15, 60-67*/
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+ char firmware_ver[16]; /*17, 68-83*/
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+ char device_map[16]; /*21, 84-99*/
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};
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};
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/* signature of set and get firmware config */
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/* signature of set and get firmware config */
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-#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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-#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
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+#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
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+#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
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/* message code of inbound message register */
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/* message code of inbound message register */
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-#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
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-#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
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+#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
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+#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
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#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
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#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
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#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
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#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
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#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
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#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
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@@ -203,6 +210,60 @@ struct FIRMWARE_INFO
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#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
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#define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000
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/* outbound firmware ok */
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/* outbound firmware ok */
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
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+
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+/*
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+************************************************************************
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+** SPEC. for Areca Type B adapter
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+************************************************************************
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+*/
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+/* ARECA HBB COMMAND for its FIRMWARE */
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+/* window of "instruction flags" from driver to iop */
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+#define ARCMSR_DRV2IOP_DOORBELL 0x00020400
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+#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
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+/* window of "instruction flags" from iop to driver */
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+#define ARCMSR_IOP2DRV_DOORBELL 0x00020408
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+#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
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+/* ARECA FLAG LANGUAGE */
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+/* ioctl transfer */
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+#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
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+/* ioctl transfer */
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+#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
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+#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
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+#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
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+
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+#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
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+#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
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+#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
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+/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
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+/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
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+/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
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+/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
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+/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
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+/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
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+#define ARCMSR_MESSAGE_START_BGRB 0x00060008
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+#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
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+#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
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+/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
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+#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
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+/* ioctl transfer */
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+#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
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+/* ioctl transfer */
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+#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
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+#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
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+#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
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+
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+/* data tunnel buffer between user space program and its firmware */
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+/* user space data to iop 128bytes */
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+#define ARCMSR_IOCTL_WBUFFER 0x0000fe00
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+/* iop data to user space 128bytes */
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+#define ARCMSR_IOCTL_RBUFFER 0x0000ff00
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+/* iop message_rwbuffer for message command */
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+#define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
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@@ -214,7 +275,6 @@ struct ARCMSR_CDB
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uint8_t TargetID;
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uint8_t TargetID;
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uint8_t LUN;
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uint8_t LUN;
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uint8_t Function;
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uint8_t Function;
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-
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uint8_t CdbLength;
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uint8_t CdbLength;
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uint8_t sgcount;
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uint8_t sgcount;
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uint8_t Flags;
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uint8_t Flags;
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@@ -224,20 +284,18 @@ struct ARCMSR_CDB
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#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
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#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
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#define ARCMSR_CDB_FLAG_HEADQ 0x08
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#define ARCMSR_CDB_FLAG_HEADQ 0x08
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#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
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#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
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- uint8_t Reserved1;
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+ uint8_t Reserved1;
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uint32_t Context;
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uint32_t Context;
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uint32_t DataLength;
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uint32_t DataLength;
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-
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uint8_t Cdb[16];
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uint8_t Cdb[16];
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-
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uint8_t DeviceStatus;
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uint8_t DeviceStatus;
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-#define ARCMSR_DEV_CHECK_CONDITION 0x02
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-#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
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-#define ARCMSR_DEV_ABORTED 0xF1
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-#define ARCMSR_DEV_INIT_FAIL 0xF2
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- uint8_t SenseData[15];
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+#define ARCMSR_DEV_CHECK_CONDITION 0x02
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+#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
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+#define ARCMSR_DEV_ABORTED 0xF1
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+#define ARCMSR_DEV_INIT_FAIL 0xF2
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+ uint8_t SenseData[15];
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union
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union
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{
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{
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struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
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struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES];
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@@ -246,10 +304,10 @@ struct ARCMSR_CDB
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};
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};
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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-** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
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+** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
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*******************************************************************************
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*******************************************************************************
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*/
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*/
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-struct MessageUnit
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+struct MessageUnit_A
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{
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{
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uint32_t resrved0[4]; /*0000 000F*/
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uint32_t resrved0[4]; /*0000 000F*/
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uint32_t inbound_msgaddr0; /*0010 0013*/
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uint32_t inbound_msgaddr0; /*0010 0013*/
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@@ -274,6 +332,30 @@ struct MessageUnit
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uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
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uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
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uint32_t reserved6[32]; /*0F80 0FFF 32*/
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uint32_t reserved6[32]; /*0F80 0FFF 32*/
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};
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};
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+
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+struct MessageUnit_B
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+{
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+ uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
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+ uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
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+ uint32_t postq_index;
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+ uint32_t doneq_index;
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+ uint32_t *drv2iop_doorbell_reg;
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+ uint32_t *drv2iop_doorbell_mask_reg;
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+ uint32_t *iop2drv_doorbell_reg;
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+ uint32_t *iop2drv_doorbell_mask_reg;
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+ uint32_t *msgcode_rwbuffer_reg;
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+ uint32_t *ioctl_wbuffer_reg;
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+ uint32_t *ioctl_rbuffer_reg;
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+};
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+
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+struct MessageUnit
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+{
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+ union
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+ {
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+ struct MessageUnit_A pmu_A;
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+ struct MessageUnit_B pmu_B;
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+ } u;
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+};
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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** Adapter Control Block
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** Adapter Control Block
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@@ -281,37 +363,45 @@ struct MessageUnit
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*/
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*/
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struct AdapterControlBlock
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struct AdapterControlBlock
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{
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{
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+ uint32_t adapter_type; /* adapter A,B..... */
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+ #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
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+ #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
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+ #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */
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+ #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
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struct pci_dev * pdev;
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struct pci_dev * pdev;
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struct Scsi_Host * host;
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struct Scsi_Host * host;
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unsigned long vir2phy_offset;
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unsigned long vir2phy_offset;
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/* Offset is used in making arc cdb physical to virtual calculations */
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/* Offset is used in making arc cdb physical to virtual calculations */
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uint32_t outbound_int_enable;
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uint32_t outbound_int_enable;
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- struct MessageUnit __iomem * pmu;
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+ struct MessageUnit * pmu;
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/* message unit ATU inbound base address0 */
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/* message unit ATU inbound base address0 */
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uint32_t acb_flags;
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uint32_t acb_flags;
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-#define ACB_F_SCSISTOPADAPTER 0x0001
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-#define ACB_F_MSG_STOP_BGRB 0x0002
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+ #define ACB_F_SCSISTOPADAPTER 0x0001
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+ #define ACB_F_MSG_STOP_BGRB 0x0002
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/* stop RAID background rebuild */
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/* stop RAID background rebuild */
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-#define ACB_F_MSG_START_BGRB 0x0004
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+ #define ACB_F_MSG_START_BGRB 0x0004
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/* stop RAID background rebuild */
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/* stop RAID background rebuild */
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-#define ACB_F_IOPDATA_OVERFLOW 0x0008
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+ #define ACB_F_IOPDATA_OVERFLOW 0x0008
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/* iop message data rqbuffer overflow */
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/* iop message data rqbuffer overflow */
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-#define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
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+ #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
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/* message clear wqbuffer */
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/* message clear wqbuffer */
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-#define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
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+ #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
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/* message clear rqbuffer */
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/* message clear rqbuffer */
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-#define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
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-#define ACB_F_BUS_RESET 0x0080
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-#define ACB_F_IOP_INITED 0x0100
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+ #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
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+ #define ACB_F_BUS_RESET 0x0080
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+ #define ACB_F_IOP_INITED 0x0100
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/* iop init */
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/* iop init */
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struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
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struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
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/* used for memory free */
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/* used for memory free */
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struct list_head ccb_free_list;
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struct list_head ccb_free_list;
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/* head of free ccb list */
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/* head of free ccb list */
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+
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atomic_t ccboutstandingcount;
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atomic_t ccboutstandingcount;
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+ /*The present outstanding command number that in the IOP that
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+ waiting for being handled by FW*/
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void * dma_coherent;
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void * dma_coherent;
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/* dma_coherent used for memory free */
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/* dma_coherent used for memory free */
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@@ -353,7 +443,7 @@ struct CommandControlBlock
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{
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{
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struct ARCMSR_CDB arcmsr_cdb;
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struct ARCMSR_CDB arcmsr_cdb;
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/*
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/*
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- ** 0-503 (size of CDB=504):
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+ ** 0-503 (size of CDB = 504):
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** arcmsr messenger scsi command descriptor size 504 bytes
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** arcmsr messenger scsi command descriptor size 504 bytes
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*/
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*/
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uint32_t cdb_shifted_phyaddr;
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uint32_t cdb_shifted_phyaddr;
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@@ -466,7 +556,9 @@ struct SENSE_DATA
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#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
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#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
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#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
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#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
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-extern void arcmsr_post_Qbuffer(struct AdapterControlBlock *acb);
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+extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *);
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+extern void arcmsr_iop_message_read(struct AdapterControlBlock *);
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+extern struct QBUFFER *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
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extern struct class_device_attribute *arcmsr_host_attrs[];
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extern struct class_device_attribute *arcmsr_host_attrs[];
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-extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *acb);
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+extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
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void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
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void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);
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