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@@ -1449,7 +1449,7 @@ static void sky2_rx_start(struct sky2_port *sky2)
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sky2_qset(hw, rxq);
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/* On PCI express lowering the watermark gives better performance */
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- if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
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+ if (pci_is_pcie(hw->pdev))
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sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
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/* These chips have no ram buffer?
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@@ -3072,7 +3072,7 @@ static void sky2_reset(struct sky2_hw *hw)
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{
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struct pci_dev *pdev = hw->pdev;
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u16 status;
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- int i, cap;
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+ int i;
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u32 hwe_mask = Y2_HWE_ALL_MASK;
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/* disable ASF */
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@@ -3108,8 +3108,7 @@ static void sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, B0_CTST, CS_MRST_CLR);
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- cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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- if (cap) {
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+ if (pci_is_pcie(pdev)) {
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sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
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0xfffffffful);
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@@ -3171,11 +3170,11 @@ static void sky2_reset(struct sky2_hw *hw)
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/* check if PSMv2 was running before */
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reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
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- if (reg & PCI_EXP_LNKCTL_ASPMC) {
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- cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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+ if (reg & PCI_EXP_LNKCTL_ASPMC)
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/* restore the PCIe Link Control register */
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- sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
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- }
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+ sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
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+ reg);
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+
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
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