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@@ -28,31 +28,27 @@
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#define TVP7002_MODULE_NAME "tvp7002"
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-/* Platform-dependent data
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- *
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- * clk_polarity:
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- * 0 -> data clocked out on rising edge of DATACLK signal
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- * 1 -> data clocked out on falling edge of DATACLK signal
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- * hs_polarity:
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- * 0 -> active low HSYNC output
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- * 1 -> active high HSYNC output
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- * sog_polarity:
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- * 0 -> normal operation
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- * 1 -> operation with polarity inverted
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- * vs_polarity:
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- * 0 -> active low VSYNC output
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- * 1 -> active high VSYNC output
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- * fid_polarity:
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- * 0 -> the field ID output is set to logic 1 for an odd
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- * field (field 1) and set to logic 0 for an even
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- * field (field 0).
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- * 1 -> operation with polarity inverted.
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+/**
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+ * struct tvp7002_config - Platform dependent data
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+ *@clk_polarity: Clock polarity
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+ * 0 - Data clocked out on rising edge of DATACLK signal
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+ * 1 - Data clocked out on falling edge of DATACLK signal
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+ *@hs_polarity: HSYNC polarity
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+ * 0 - Active low HSYNC output, 1 - Active high HSYNC output
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+ *@vs_polarity: VSYNC Polarity
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+ * 0 - Active low VSYNC output, 1 - Active high VSYNC output
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+ *@fid_polarity: Active-high Field ID polarity.
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+ * 0 - The field ID output is set to logic 1 for an odd field
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+ * (field 1) and set to logic 0 for an even field (field 0).
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+ * 1 - Operation with polarity inverted.
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+ *@sog_polarity: Active high Sync on Green output polarity.
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+ * 0 - Normal operation, 1 - Operation with polarity inverted
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*/
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struct tvp7002_config {
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- u8 clk_polarity;
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- u8 hs_polarity;
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- u8 vs_polarity;
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- u8 fid_polarity;
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- u8 sog_polarity;
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+ bool clk_polarity;
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+ bool hs_polarity;
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+ bool vs_polarity;
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+ bool fid_polarity;
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+ bool sog_polarity;
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};
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#endif
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