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@@ -5,6 +5,7 @@
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/thread_info.h>
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+#include <asm/v7m.h>
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@ Bad Abort numbers
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@ -----------------
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@@ -44,6 +45,116 @@
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#endif
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.endm
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+#ifdef CONFIG_CPU_V7M
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+/*
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+ * ARMv7-M exception entry/exit macros.
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+ *
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+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
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+ * automatically saved on the current stack (32 words) before
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+ * switching to the exception stack (SP_main).
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+ *
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+ * If exception is taken while in user mode, SP_main is
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+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
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+ * (CCR.STKALIGN set).
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+ *
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+ * Linux assumes that the interrupts are disabled when entering an
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+ * exception handler and it may BUG if this is not the case. Interrupts
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+ * are disabled during entry and reenabled in the exit macro.
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+ *
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+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
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+ * When returning to kernel mode, we don't return from exception.
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+ */
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+ .macro v7m_exception_entry
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+ @ determine the location of the registers saved by the core during
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+ @ exception entry. Depending on the mode the cpu was in when the
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+ @ exception happend that is either on the main or the process stack.
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+ @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
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+ @ was used.
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+ tst lr, #EXC_RET_STACK_MASK
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+ mrsne r12, psp
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+ moveq r12, sp
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+
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+ @ we cannot rely on r0-r3 and r12 matching the value saved in the
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+ @ exception frame because of tail-chaining. So these have to be
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+ @ reloaded.
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+ ldmia r12!, {r0-r3}
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+
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+ @ Linux expects to have irqs off. Do it here before taking stack space
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+ cpsid i
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+
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+ sub sp, #S_FRAME_SIZE-S_IP
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+ stmdb sp!, {r0-r11}
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+
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+ @ load saved r12, lr, return address and xPSR.
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+ @ r0-r7 are used for signals and never touched from now on. Clobbering
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+ @ r8-r12 is OK.
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+ mov r9, r12
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+ ldmia r9!, {r8, r10-r12}
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+
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+ @ calculate the original stack pointer value.
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+ @ r9 currently points to the memory location just above the auto saved
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+ @ xPSR.
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+ @ The cpu might automatically 8-byte align the stack. Bit 9
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+ @ of the saved xPSR specifies if stack aligning took place. In this case
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+ @ another 32-bit value is included in the stack.
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+
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+ tst r12, V7M_xPSR_FRAMEPTRALIGN
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+ addne r9, r9, #4
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+
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+ @ store saved r12 using str to have a register to hold the base for stm
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+ str r8, [sp, #S_IP]
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+ add r8, sp, #S_SP
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+ @ store r13-r15, xPSR
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+ stmia r8!, {r9-r12}
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+ @ store old_r0
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+ str r0, [r8]
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+ .endm
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+
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+ /*
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+ * PENDSV and SVCALL are configured to have the same exception
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+ * priorities. As a kernel thread runs at SVCALL execution priority it
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+ * can never be preempted and so we will never have to return to a
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+ * kernel thread here.
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+ */
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+ .macro v7m_exception_slow_exit ret_r0
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+ cpsid i
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+ ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
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+
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+ @ read original r12, sp, lr, pc and xPSR
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+ add r12, sp, #S_IP
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+ ldmia r12, {r1-r5}
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+
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+ @ an exception frame is always 8-byte aligned. To tell the hardware if
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+ @ the sp to be restored is aligned or not set bit 9 of the saved xPSR
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+ @ accordingly.
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+ tst r2, #4
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+ subne r2, r2, #4
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+ orrne r5, V7M_xPSR_FRAMEPTRALIGN
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+ biceq r5, V7M_xPSR_FRAMEPTRALIGN
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+
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+ @ write basic exception frame
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+ stmdb r2!, {r1, r3-r5}
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+ ldmia sp, {r1, r3-r5}
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+ .if \ret_r0
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+ stmdb r2!, {r0, r3-r5}
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+ .else
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+ stmdb r2!, {r1, r3-r5}
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+ .endif
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+
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+ @ restore process sp
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+ msr psp, r2
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+
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+ @ restore original r4-r11
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+ ldmia sp!, {r0-r11}
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+
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+ @ restore main sp
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+ add sp, sp, #S_FRAME_SIZE-S_IP
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+
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+ cpsie i
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+ bx lr
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+ .endm
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+#endif /* CONFIG_CPU_V7M */
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+
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@
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@ Store/load the USER SP and LR registers by switching to the SYS
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@ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
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@@ -131,6 +242,18 @@
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rfeia sp!
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.endm
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+#ifdef CONFIG_CPU_V7M
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+ /*
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+ * Note we don't need to do clrex here as clearing the local monitor is
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+ * part of each exception entry and exit sequence.
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+ */
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+ .macro restore_user_regs, fast = 0, offset = 0
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+ .if \offset
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+ add sp, #\offset
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+ .endif
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+ v7m_exception_slow_exit ret_r0 = \fast
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+ .endm
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+#else /* ifdef CONFIG_CPU_V7M */
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.macro restore_user_regs, fast = 0, offset = 0
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clrex @ clear the exclusive monitor
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mov r2, sp
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@@ -147,6 +270,7 @@
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add sp, sp, #S_FRAME_SIZE - S_SP
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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+#endif /* ifdef CONFIG_CPU_V7M / else */
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.macro get_thread_info, rd
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mov \rd, sp
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Uwe Kleine-König