|
@@ -944,9 +944,9 @@ __kuser_helper_end:
|
|
|
/*
|
|
|
* Vector stubs.
|
|
|
*
|
|
|
- * This code is copied to 0xffff0200 so we can use branches in the
|
|
|
- * vectors, rather than ldr's. Note that this code must not
|
|
|
- * exceed 0x300 bytes.
|
|
|
+ * This code is copied to 0xffff1000 so we can use branches in the
|
|
|
+ * vectors, rather than ldr's. Note that this code must not exceed
|
|
|
+ * a page size.
|
|
|
*
|
|
|
* Common stub entry macro:
|
|
|
* Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
|
|
@@ -995,6 +995,15 @@ ENDPROC(vector_\name)
|
|
|
|
|
|
.globl __stubs_start
|
|
|
__stubs_start:
|
|
|
+ @ This must be the first word
|
|
|
+ .word vector_swi
|
|
|
+
|
|
|
+vector_rst:
|
|
|
+ ARM( swi SYS_ERROR0 )
|
|
|
+ THUMB( svc #0 )
|
|
|
+ THUMB( nop )
|
|
|
+ b vector_und
|
|
|
+
|
|
|
/*
|
|
|
* Interrupt dispatcher
|
|
|
*/
|
|
@@ -1088,6 +1097,16 @@ __stubs_start:
|
|
|
|
|
|
.align 5
|
|
|
|
|
|
+/*=============================================================================
|
|
|
+ * Address exception handler
|
|
|
+ *-----------------------------------------------------------------------------
|
|
|
+ * These aren't too critical.
|
|
|
+ * (they're not supposed to happen, and won't happen in 32-bit data mode).
|
|
|
+ */
|
|
|
+
|
|
|
+vector_addrexcptn:
|
|
|
+ b vector_addrexcptn
|
|
|
+
|
|
|
/*=============================================================================
|
|
|
* Undefined FIQs
|
|
|
*-----------------------------------------------------------------------------
|
|
@@ -1101,35 +1120,14 @@ __stubs_start:
|
|
|
vector_fiq:
|
|
|
subs pc, lr, #4
|
|
|
|
|
|
-/*=============================================================================
|
|
|
- * Address exception handler
|
|
|
- *-----------------------------------------------------------------------------
|
|
|
- * These aren't too critical.
|
|
|
- * (they're not supposed to happen, and won't happen in 32-bit data mode).
|
|
|
- */
|
|
|
-
|
|
|
-vector_addrexcptn:
|
|
|
- b vector_addrexcptn
|
|
|
-
|
|
|
-/*
|
|
|
- * We group all the following data together to optimise
|
|
|
- * for CPUs with separate I & D caches.
|
|
|
- */
|
|
|
- .align 5
|
|
|
-
|
|
|
-.LCvswi:
|
|
|
- .word vector_swi
|
|
|
-
|
|
|
.globl __stubs_end
|
|
|
__stubs_end:
|
|
|
|
|
|
- .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
|
|
|
+ .equ stubs_offset, __vectors_start + 0x1000 - __stubs_start
|
|
|
|
|
|
.globl __vectors_start
|
|
|
__vectors_start:
|
|
|
- ARM( swi SYS_ERROR0 )
|
|
|
- THUMB( svc #0 )
|
|
|
- THUMB( nop )
|
|
|
+ W(b) vector_rst + stubs_offset
|
|
|
W(b) vector_und + stubs_offset
|
|
|
W(ldr) pc, .LCvswi + stubs_offset
|
|
|
W(b) vector_pabt + stubs_offset
|