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@@ -472,61 +472,14 @@ static void vlv_init_dpio(struct drm_device *dev)
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POSTING_READ(DPIO_CTL);
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}
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-static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
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-{
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- DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
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- return 1;
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-}
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-
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-static const struct dmi_system_id intel_dual_link_lvds[] = {
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- {
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- .callback = intel_dual_link_lvds_callback,
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- .ident = "Apple MacBook Pro (Core i5/i7 Series)",
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- .matches = {
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- DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
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- DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
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- },
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- },
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- { } /* terminating entry */
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-};
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-
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-static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
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- unsigned int reg)
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-{
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- unsigned int val;
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-
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- /* use the module option value if specified */
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- if (i915_lvds_channel_mode > 0)
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- return i915_lvds_channel_mode == 2;
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-
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- if (dmi_check_system(intel_dual_link_lvds))
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- return true;
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-
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- if (dev_priv->lvds_val)
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- val = dev_priv->lvds_val;
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- else {
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- /* BIOS should set the proper LVDS register value at boot, but
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- * in reality, it doesn't set the value when the lid is closed;
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- * we need to check "the value to be set" in VBT when LVDS
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- * register is uninitialized.
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- */
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- val = I915_READ(reg);
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- if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
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- val = dev_priv->bios_lvds_val;
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- dev_priv->lvds_val = val;
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- }
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- return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
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-}
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-
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static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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int refclk)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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- if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
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+ if (intel_is_dual_link_lvds(dev)) {
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/* LVDS dual channel */
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if (refclk == 100000)
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limit = &intel_limits_ironlake_dual_lvds_100m;
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@@ -550,11 +503,10 @@ static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
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static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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const intel_limit_t *limit;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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- if (is_dual_link_lvds(dev_priv, LVDS))
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+ if (intel_is_dual_link_lvds(dev))
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/* LVDS with dual channel */
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limit = &intel_limits_g4x_dual_channel_lvds;
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else
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@@ -686,7 +638,6 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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intel_clock_t clock;
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int err = target;
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@@ -696,7 +647,7 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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* We haven't figured out how to reliably set up different
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* single/dual channel state, if we even can.
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*/
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- if (is_dual_link_lvds(dev_priv, LVDS))
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+ if (intel_is_dual_link_lvds(dev))
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clock.p2 = limit->p2.p2_fast;
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else
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clock.p2 = limit->p2.p2_slow;
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@@ -749,7 +700,6 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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intel_clock_t *best_clock)
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{
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struct drm_device *dev = crtc->dev;
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- struct drm_i915_private *dev_priv = dev->dev_private;
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intel_clock_t clock;
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int max_n;
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bool found;
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@@ -764,7 +714,7 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
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lvds_reg = PCH_LVDS;
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else
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lvds_reg = LVDS;
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- if (is_dual_link_lvds(dev_priv, lvds_reg))
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+ if (intel_is_dual_link_lvds(dev))
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clock.p2 = limit->p2.p2_fast;
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else
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clock.p2 = limit->p2.p2_slow;
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@@ -5356,7 +5306,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
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if (is_lvds) {
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if ((intel_panel_use_ssc(dev_priv) &&
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dev_priv->lvds_ssc_freq == 100) ||
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- is_dual_link_lvds(dev_priv, PCH_LVDS))
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+ intel_is_dual_link_lvds(dev))
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factor = 25;
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} else if (is_sdvo && is_tv)
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factor = 20;
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