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@@ -47,58 +47,6 @@ void __iomem *prcm_mpu_base;
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#define MAX_MODULE_ENABLE_WAIT 100000
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-/* Resets clock rates and reboots the system. Only called from system.h */
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-void omap_prcm_restart(char mode, const char *cmd)
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-{
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- s16 prcm_offs = 0;
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-
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- if (cpu_is_omap24xx()) {
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- omap2xxx_clk_prepare_for_reboot();
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-
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- prcm_offs = WKUP_MOD;
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- } else if (cpu_is_omap34xx()) {
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- prcm_offs = OMAP3430_GR_MOD;
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- omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
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- } else if (cpu_is_omap44xx()) {
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- omap4_prminst_global_warm_sw_reset(); /* never returns */
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- } else {
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- WARN_ON(1);
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- }
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-
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- /*
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- * As per Errata i520, in some cases, user will not be able to
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- * access DDR memory after warm-reset.
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- * This situation occurs while the warm-reset happens during a read
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- * access to DDR memory. In that particular condition, DDR memory
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- * does not respond to a corrupted read command due to the warm
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- * reset occurrence but SDRC is waiting for read completion.
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- * SDRC is not sensitive to the warm reset, but the interconnect is
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- * reset on the fly, thus causing a misalignment between SDRC logic,
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- * interconnect logic and DDR memory state.
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- * WORKAROUND:
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- * Steps to perform before a Warm reset is trigged:
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- * 1. enable self-refresh on idle request
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- * 2. put SDRC in idle
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- * 3. wait until SDRC goes to idle
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- * 4. generate SW reset (Global SW reset)
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- *
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- * Steps to be performed after warm reset occurs (in bootloader):
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- * if HW warm reset is the source, apply below steps before any
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- * accesses to SDRAM:
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- * 1. Reset SMS and SDRC and wait till reset is complete
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- * 2. Re-initialize SMS, SDRC and memory
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- *
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- * NOTE: Above work around is required only if arch reset is implemented
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- * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
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- * the WA since it resets SDRC as well as part of cold reset.
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- */
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-
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- /* XXX should be moved to some OMAP2/3 specific code */
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- omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
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- OMAP2_RM_RSTCTRL);
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- omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
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-}
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-
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/**
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* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
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* @reg: physical address of module IDLEST register
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