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@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
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int i, cpu = 1, boot_cpu = 0;
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#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
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+ int cpu_hw_intr;
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+
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/* arbitration priority */
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clear_c0_brcm_cmt_ctrl(0x30);
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@@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void)
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* MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
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* MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
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*/
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- change_c0_brcm_cmt_intr(0xf8018000,
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- (0x02 << 27) | (0x03 << 15));
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+ if (boot_cpu == 0)
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+ cpu_hw_intr = 0x02;
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+ else
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+ cpu_hw_intr = 0x1d;
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+
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+ change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
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/* single core, 2 threads (2 pipelines) */
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max_cpus = 2;
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