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@@ -262,7 +262,7 @@ static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
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u32 reg;
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rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
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- return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
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+ return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
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}
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#else
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#define rt61pci_rfkill_poll NULL
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@@ -990,49 +990,49 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
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}
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static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
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- struct data_entry *entry)
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+ struct queue_entry *entry)
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{
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- __le32 *rxd = entry->priv;
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+ struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
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u32 word;
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- rt2x00_desc_read(rxd, 5, &word);
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- rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
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- entry->data_dma);
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- rt2x00_desc_write(rxd, 5, word);
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+ rt2x00_desc_read(priv_rx->desc, 5, &word);
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+ rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, priv_rx->dma);
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+ rt2x00_desc_write(priv_rx->desc, 5, word);
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- rt2x00_desc_read(rxd, 0, &word);
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+ rt2x00_desc_read(priv_rx->desc, 0, &word);
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rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
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- rt2x00_desc_write(rxd, 0, word);
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+ rt2x00_desc_write(priv_rx->desc, 0, word);
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}
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static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
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- struct data_entry *entry)
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+ struct queue_entry *entry)
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{
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- __le32 *txd = entry->priv;
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+ struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
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u32 word;
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- rt2x00_desc_read(txd, 1, &word);
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+ rt2x00_desc_read(priv_tx->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
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- rt2x00_desc_write(txd, 1, word);
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+ rt2x00_desc_write(priv_tx->desc, 1, word);
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- rt2x00_desc_read(txd, 5, &word);
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- rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->ring->queue_idx);
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+ rt2x00_desc_read(priv_tx->desc, 5, &word);
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+ rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
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rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
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- rt2x00_desc_write(txd, 5, word);
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+ rt2x00_desc_write(priv_tx->desc, 5, word);
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- rt2x00_desc_read(txd, 6, &word);
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- rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
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- entry->data_dma);
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- rt2x00_desc_write(txd, 6, word);
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+ rt2x00_desc_read(priv_tx->desc, 6, &word);
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+ rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, priv_tx->dma);
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+ rt2x00_desc_write(priv_tx->desc, 6, word);
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- rt2x00_desc_read(txd, 0, &word);
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+ rt2x00_desc_read(priv_tx->desc, 0, &word);
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rt2x00_set_field32(&word, TXD_W0_VALID, 0);
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rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
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- rt2x00_desc_write(txd, 0, word);
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+ rt2x00_desc_write(priv_tx->desc, 0, word);
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}
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-static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
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+static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
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{
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+ struct queue_entry_priv_pci_rx *priv_rx;
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+ struct queue_entry_priv_pci_tx *priv_tx;
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u32 reg;
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/*
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@@ -1040,59 +1040,50 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
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*/
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rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
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rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
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+ rt2x00dev->tx[0].limit);
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rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
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+ rt2x00dev->tx[1].limit);
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rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
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+ rt2x00dev->tx[2].limit);
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rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
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+ rt2x00dev->tx[3].limit);
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rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
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rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
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- rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
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rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
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- 4);
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+ rt2x00dev->tx[0].desc_size / 4);
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rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
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+ priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
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- rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
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+ rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
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+ priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
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- rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
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+ rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
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+ priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
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- rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
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+ rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
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+ priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
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- rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
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+ rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, priv_tx->dma);
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rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
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- rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
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- rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
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- rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
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- rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
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-
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rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
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- rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
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- rt2x00dev->rx->stats.limit);
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+ rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
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rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
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rt2x00dev->rx->desc_size / 4);
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rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
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rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
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+ priv_rx = rt2x00dev->rx->entries[0].priv_data;
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rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
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- rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
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- rt2x00dev->rx->data_dma);
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+ rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, priv_rx->dma);
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rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
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rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
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@@ -1108,7 +1099,7 @@ static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
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rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
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rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
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rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
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- rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
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+ rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 0);
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rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
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rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
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@@ -1375,7 +1366,7 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
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/*
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* Initialize all registers.
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*/
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- if (rt61pci_init_rings(rt2x00dev) ||
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+ if (rt61pci_init_queues(rt2x00dev) ||
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rt61pci_init_registers(rt2x00dev) ||
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rt61pci_init_bbp(rt2x00dev)) {
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ERROR(rt2x00dev, "Register initialization failed.\n");
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@@ -1508,10 +1499,10 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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*/
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static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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struct sk_buff *skb,
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- struct txdata_entry_desc *desc,
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+ struct txentry_desc *txdesc,
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struct ieee80211_tx_control *control)
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{
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- struct skb_desc *skbdesc = get_skb_desc(skb);
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+ struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
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__le32 *txd = skbdesc->desc;
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u32 word;
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@@ -1519,19 +1510,19 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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* Start writing the descriptor words.
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*/
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rt2x00_desc_read(txd, 1, &word);
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- rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
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- rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
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- rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
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- rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
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+ rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
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+ rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
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+ rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
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+ rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
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rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
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rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
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rt2x00_desc_write(txd, 1, word);
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rt2x00_desc_read(txd, 2, &word);
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- rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
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- rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
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- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
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- rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
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+ rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
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+ rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
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+ rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
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+ rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
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rt2x00_desc_write(txd, 2, word);
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rt2x00_desc_read(txd, 5, &word);
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@@ -1548,21 +1539,21 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
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rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
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rt2x00_set_field32(&word, TXD_W0_VALID, 1);
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rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
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- test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
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+ test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_ACK,
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- test_bit(ENTRY_TXD_ACK, &desc->flags));
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+ test_bit(ENTRY_TXD_ACK, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
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- test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
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+ test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_OFDM,
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- test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
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- rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
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+ test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
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+ rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
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rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
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!!(control->flags &
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IEEE80211_TXCTL_LONG_RETRY_LIMIT));
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rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
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rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
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rt2x00_set_field32(&word, TXD_W0_BURST,
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- test_bit(ENTRY_TXD_BURST, &desc->flags));
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+ test_bit(ENTRY_TXD_BURST, &txdesc->flags));
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rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
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rt2x00_desc_write(txd, 0, word);
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}
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@@ -1648,28 +1639,28 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
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return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
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}
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-static void rt61pci_fill_rxdone(struct data_entry *entry,
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- struct rxdata_entry_desc *desc)
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+static void rt61pci_fill_rxdone(struct queue_entry *entry,
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+ struct rxdone_entry_desc *rxdesc)
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{
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- __le32 *rxd = entry->priv;
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+ struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
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u32 word0;
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u32 word1;
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- rt2x00_desc_read(rxd, 0, &word0);
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- rt2x00_desc_read(rxd, 1, &word1);
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+ rt2x00_desc_read(priv_rx->desc, 0, &word0);
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+ rt2x00_desc_read(priv_rx->desc, 1, &word1);
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- desc->flags = 0;
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+ rxdesc->flags = 0;
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if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
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- desc->flags |= RX_FLAG_FAILED_FCS_CRC;
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+ rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
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/*
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* Obtain the status about this packet.
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*/
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- desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
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- desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
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- desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
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- desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
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- desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
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+ rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
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+ rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
|
|
|
+ rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
|
|
|
+ rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
|
|
|
+ rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -1677,17 +1668,16 @@ static void rt61pci_fill_rxdone(struct data_entry *entry,
|
|
|
*/
|
|
|
static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
|
|
|
{
|
|
|
- struct data_ring *ring;
|
|
|
- struct data_entry *entry;
|
|
|
- struct data_entry *entry_done;
|
|
|
- __le32 *txd;
|
|
|
+ struct data_queue *queue;
|
|
|
+ struct queue_entry *entry;
|
|
|
+ struct queue_entry *entry_done;
|
|
|
+ struct queue_entry_priv_pci_tx *priv_tx;
|
|
|
+ struct txdone_entry_desc txdesc;
|
|
|
u32 word;
|
|
|
u32 reg;
|
|
|
u32 old_reg;
|
|
|
int type;
|
|
|
int index;
|
|
|
- int tx_status;
|
|
|
- int retry;
|
|
|
|
|
|
/*
|
|
|
* During each loop we will compare the freshly read
|
|
@@ -1710,11 +1700,11 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
|
|
|
|
|
|
/*
|
|
|
* Skip this entry when it contains an invalid
|
|
|
- * ring identication number.
|
|
|
+ * queue identication number.
|
|
|
*/
|
|
|
type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
|
|
|
- ring = rt2x00lib_get_ring(rt2x00dev, type);
|
|
|
- if (unlikely(!ring))
|
|
|
+ queue = rt2x00queue_get_queue(rt2x00dev, type);
|
|
|
+ if (unlikely(!queue))
|
|
|
continue;
|
|
|
|
|
|
/*
|
|
@@ -1722,36 +1712,40 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
|
|
|
* index number.
|
|
|
*/
|
|
|
index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
|
|
|
- if (unlikely(index >= ring->stats.limit))
|
|
|
+ if (unlikely(index >= queue->limit))
|
|
|
continue;
|
|
|
|
|
|
- entry = &ring->entry[index];
|
|
|
- txd = entry->priv;
|
|
|
- rt2x00_desc_read(txd, 0, &word);
|
|
|
+ entry = &queue->entries[index];
|
|
|
+ priv_tx = entry->priv_data;
|
|
|
+ rt2x00_desc_read(priv_tx->desc, 0, &word);
|
|
|
|
|
|
if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
|
|
|
!rt2x00_get_field32(word, TXD_W0_VALID))
|
|
|
return;
|
|
|
|
|
|
- entry_done = rt2x00_get_data_entry_done(ring);
|
|
|
+ entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
|
|
|
while (entry != entry_done) {
|
|
|
- /* Catch up. Just report any entries we missed as
|
|
|
- * failed. */
|
|
|
+ /* Catch up.
|
|
|
+ * Just report any entries we missed as failed.
|
|
|
+ */
|
|
|
WARNING(rt2x00dev,
|
|
|
- "TX status report missed for entry %p\n",
|
|
|
- entry_done);
|
|
|
- rt2x00pci_txdone(rt2x00dev, entry_done, TX_FAIL_OTHER,
|
|
|
- 0);
|
|
|
- entry_done = rt2x00_get_data_entry_done(ring);
|
|
|
+ "TX status report missed for entry %d\n",
|
|
|
+ entry_done->entry_idx);
|
|
|
+
|
|
|
+ txdesc.status = TX_FAIL_OTHER;
|
|
|
+ txdesc.retry = 0;
|
|
|
+
|
|
|
+ rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
|
|
|
+ entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
* Obtain the status about this packet.
|
|
|
*/
|
|
|
- tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
|
|
|
- retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
|
|
|
+ txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
|
|
|
+ txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
|
|
|
|
|
|
- rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
|
|
|
+ rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -2381,9 +2375,9 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
struct ieee80211_tx_control *control)
|
|
|
{
|
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
- struct skb_desc *desc;
|
|
|
- struct data_ring *ring;
|
|
|
- struct data_entry *entry;
|
|
|
+ struct skb_frame_desc *skbdesc;
|
|
|
+ struct data_queue *queue;
|
|
|
+ struct queue_entry *entry;
|
|
|
|
|
|
/*
|
|
|
* Just in case the ieee80211 doesn't set this,
|
|
@@ -2391,15 +2385,15 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
* initialization.
|
|
|
*/
|
|
|
control->queue = IEEE80211_TX_QUEUE_BEACON;
|
|
|
- ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
|
|
|
- entry = rt2x00_get_data_entry(ring);
|
|
|
+ queue = rt2x00queue_get_queue(rt2x00dev, control->queue);
|
|
|
+ entry = rt2x00queue_get_entry(queue, Q_INDEX);
|
|
|
|
|
|
/*
|
|
|
* We need to append the descriptor in front of the
|
|
|
* beacon frame.
|
|
|
*/
|
|
|
- if (skb_headroom(skb) < TXD_DESC_SIZE) {
|
|
|
- if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
|
|
|
+ if (skb_headroom(skb) < queue->desc_size) {
|
|
|
+ if (pskb_expand_head(skb, queue->desc_size, 0, GFP_ATOMIC)) {
|
|
|
dev_kfree_skb(skb);
|
|
|
return -ENOMEM;
|
|
|
}
|
|
@@ -2408,19 +2402,19 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
|
/*
|
|
|
* Add the descriptor in front of the skb.
|
|
|
*/
|
|
|
- skb_push(skb, ring->desc_size);
|
|
|
- memset(skb->data, 0, ring->desc_size);
|
|
|
+ skb_push(skb, queue->desc_size);
|
|
|
+ memset(skb->data, 0, queue->desc_size);
|
|
|
|
|
|
/*
|
|
|
* Fill in skb descriptor
|
|
|
*/
|
|
|
- desc = get_skb_desc(skb);
|
|
|
- desc->desc_len = ring->desc_size;
|
|
|
- desc->data_len = skb->len - ring->desc_size;
|
|
|
- desc->desc = skb->data;
|
|
|
- desc->data = skb->data + ring->desc_size;
|
|
|
- desc->ring = ring;
|
|
|
- desc->entry = entry;
|
|
|
+ skbdesc = get_skb_frame_desc(skb);
|
|
|
+ memset(skbdesc, 0, sizeof(*skbdesc));
|
|
|
+ skbdesc->data = skb->data + queue->desc_size;
|
|
|
+ skbdesc->data_len = queue->data_size;
|
|
|
+ skbdesc->desc = skb->data;
|
|
|
+ skbdesc->desc_len = queue->desc_size;
|
|
|
+ skbdesc->entry = entry;
|
|
|
|
|
|
rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
|
|
|
|
|
@@ -2479,12 +2473,34 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
|
|
|
.config = rt61pci_config,
|
|
|
};
|
|
|
|
|
|
+static const struct data_queue_desc rt61pci_queue_rx = {
|
|
|
+ .entry_num = RX_ENTRIES,
|
|
|
+ .data_size = DATA_FRAME_SIZE,
|
|
|
+ .desc_size = RXD_DESC_SIZE,
|
|
|
+ .priv_size = sizeof(struct queue_entry_priv_pci_rx),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct data_queue_desc rt61pci_queue_tx = {
|
|
|
+ .entry_num = TX_ENTRIES,
|
|
|
+ .data_size = DATA_FRAME_SIZE,
|
|
|
+ .desc_size = TXD_DESC_SIZE,
|
|
|
+ .priv_size = sizeof(struct queue_entry_priv_pci_tx),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct data_queue_desc rt61pci_queue_bcn = {
|
|
|
+ .entry_num = BEACON_ENTRIES,
|
|
|
+ .data_size = MGMT_FRAME_SIZE,
|
|
|
+ .desc_size = TXINFO_SIZE,
|
|
|
+ .priv_size = sizeof(struct queue_entry_priv_pci_tx),
|
|
|
+};
|
|
|
+
|
|
|
static const struct rt2x00_ops rt61pci_ops = {
|
|
|
.name = KBUILD_MODNAME,
|
|
|
- .rxd_size = RXD_DESC_SIZE,
|
|
|
- .txd_size = TXD_DESC_SIZE,
|
|
|
.eeprom_size = EEPROM_SIZE,
|
|
|
.rf_size = RF_SIZE,
|
|
|
+ .rx = &rt61pci_queue_rx,
|
|
|
+ .tx = &rt61pci_queue_tx,
|
|
|
+ .bcn = &rt61pci_queue_bcn,
|
|
|
.lib = &rt61pci_rt2x00_ops,
|
|
|
.hw = &rt61pci_mac80211_ops,
|
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|