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@@ -502,14 +502,23 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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u16 twiceMaxRegulatoryPower,
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u16 powerLimit)
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{
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- struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
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- u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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- static const u16 tpScaleReductionTable[5] =
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- { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
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+#define CMP_TEST_GRP \
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+ (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
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+ pEepData->ctlIndex[i]) \
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+ || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
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+ ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
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int i;
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int16_t twiceLargestAntenna;
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+ u16 twiceMinEdgePower;
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+ u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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+ u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
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+ u16 numCtlModes, *pCtlMode, ctlMode, freq;
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+ struct chan_centers centers;
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struct cal_ctl_data_4k *rep;
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+ struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
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+ static const u16 tpScaleReductionTable[5] =
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+ { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
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struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
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0, { 0, 0, 0, 0}
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};
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@@ -520,27 +529,18 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
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0, {0, 0, 0, 0}
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};
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- u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
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u16 ctlModesFor11g[] =
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{ CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
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CTL_2GHT40
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};
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- u16 numCtlModes, *pCtlMode, ctlMode, freq;
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- struct chan_centers centers;
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- int tx_chainmask;
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- u16 twiceMinEdgePower;
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-
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- tx_chainmask = ah->txchainmask;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
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-
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twiceLargestAntenna = (int16_t)min(AntennaReduction -
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twiceLargestAntenna, 0);
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maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
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-
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if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
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maxRegAllowedPower -=
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(tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
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@@ -584,6 +584,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
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bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
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(pCtlMode[ctlMode] == CTL_2GHT40);
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+
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if (isHt40CtlMode)
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freq = centers.synth_center;
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else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
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@@ -596,22 +597,17 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
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- pEepData->ctlIndex[i]; i++) {
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- if ((((cfgCtl & ~CTL_MODE_M) |
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- (pCtlMode[ctlMode] & CTL_MODE_M)) ==
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- pEepData->ctlIndex[i]) ||
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- (((cfgCtl & ~CTL_MODE_M) |
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- (pCtlMode[ctlMode] & CTL_MODE_M)) ==
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- ((pEepData->ctlIndex[i] & CTL_MODE_M) |
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- SD_NO_CTL))) {
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+ pEepData->ctlIndex[i]; i++) {
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+
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+ if (CMP_TEST_GRP) {
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rep = &(pEepData->ctlData[i]);
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- twiceMinEdgePower =
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- ath9k_hw_get_max_edge_power(freq,
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- rep->ctlEdges[ar5416_get_ntxchains
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- (tx_chainmask) - 1],
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- IS_CHAN_2GHZ(chan),
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- AR5416_EEP4K_NUM_BAND_EDGES);
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+ twiceMinEdgePower = ath9k_hw_get_max_edge_power(
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+ freq,
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+ rep->ctlEdges[
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+ ar5416_get_ntxchains(ah->txchainmask) - 1],
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+ IS_CHAN_2GHZ(chan),
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+ AR5416_EEP4K_NUM_BAND_EDGES);
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if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
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twiceMaxEdgePower =
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@@ -628,42 +624,38 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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switch (pCtlMode[ctlMode]) {
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case CTL_11B:
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- for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
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- i++) {
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+ for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
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targetPowerCck.tPow2x[i] =
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min((u16)targetPowerCck.tPow2x[i],
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minCtlPower);
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}
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break;
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case CTL_11G:
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- for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
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- i++) {
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+ for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
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targetPowerOfdm.tPow2x[i] =
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min((u16)targetPowerOfdm.tPow2x[i],
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minCtlPower);
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}
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break;
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case CTL_2GHT20:
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- for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
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- i++) {
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+ for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
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targetPowerHt20.tPow2x[i] =
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min((u16)targetPowerHt20.tPow2x[i],
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minCtlPower);
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}
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break;
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case CTL_11B_EXT:
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- targetPowerCckExt.tPow2x[0] = min((u16)
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- targetPowerCckExt.tPow2x[0],
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- minCtlPower);
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+ targetPowerCckExt.tPow2x[0] =
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+ min((u16)targetPowerCckExt.tPow2x[0],
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+ minCtlPower);
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break;
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case CTL_11G_EXT:
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- targetPowerOfdmExt.tPow2x[0] = min((u16)
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- targetPowerOfdmExt.tPow2x[0],
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- minCtlPower);
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+ targetPowerOfdmExt.tPow2x[0] =
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+ min((u16)targetPowerOfdmExt.tPow2x[0],
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+ minCtlPower);
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break;
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case CTL_2GHT40:
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- for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
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- i++) {
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+ for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
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targetPowerHt40.tPow2x[i] =
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min((u16)targetPowerHt40.tPow2x[i],
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minCtlPower);
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@@ -674,9 +666,13 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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}
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}
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- ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
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- ratesArray[rate18mb] = ratesArray[rate24mb] =
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- targetPowerOfdm.tPow2x[0];
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+ ratesArray[rate6mb] =
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+ ratesArray[rate9mb] =
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+ ratesArray[rate12mb] =
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+ ratesArray[rate18mb] =
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+ ratesArray[rate24mb] =
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+ targetPowerOfdm.tPow2x[0];
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+
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ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
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ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
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ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
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@@ -700,6 +696,8 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
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ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
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ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
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}
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+
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+#undef CMP_TEST_GRP
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}
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static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
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