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@@ -535,23 +535,27 @@ static int __init da850_evm_config_emac(void)
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cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG);
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- /* configure the CFGCHIP3 register for RMII or MII */
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val = __raw_readl(cfg_chip3_base);
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- if (rmii_en)
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+
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+ if (rmii_en) {
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val |= BIT(8);
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- else
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+ ret = da8xx_pinmux_setup(da850_rmii_pins);
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+ pr_info("EMAC: RMII PHY configured, MII PHY will not be"
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+ " functional\n");
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+ } else {
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val &= ~BIT(8);
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-
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- __raw_writel(val, cfg_chip3_base);
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-
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- if (!rmii_en)
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ret = da8xx_pinmux_setup(da850_cpgmac_pins);
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- else
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- ret = da8xx_pinmux_setup(da850_rmii_pins);
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+ pr_info("EMAC: MII PHY configured, RMII PHY will not be"
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+ " functional\n");
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+ }
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+
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if (ret)
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pr_warning("da850_evm_init: cpgmac/rmii mux setup failed: %d\n",
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ret);
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+ /* configure the CFGCHIP3 register for RMII or MII */
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+ __raw_writel(val, cfg_chip3_base);
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+
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ret = davinci_cfg_reg(DA850_GPIO2_6);
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if (ret)
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pr_warning("da850_evm_init:GPIO(2,6) mux setup "
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@@ -564,17 +568,8 @@ static int __init da850_evm_config_emac(void)
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return ret;
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}
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- if (rmii_en) {
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- /* Disable MII MDIO clock */
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- gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 1);
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- pr_info("EMAC: RMII PHY configured, MII PHY will not be"
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- " functional\n");
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- } else {
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- /* Enable MII MDIO clock */
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- gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, 0);
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- pr_info("EMAC: MII PHY configured, RMII PHY will not be"
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- " functional\n");
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- }
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+ /* Enable/Disable MII MDIO clock */
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+ gpio_direction_output(DA850_MII_MDIO_CLKEN_PIN, rmii_en);
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soc_info->emac_pdata->phy_mask = DA850_EVM_PHY_MASK;
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soc_info->emac_pdata->mdio_max_freq = DA850_EVM_MDIO_FREQUENCY;
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