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@@ -2041,7 +2041,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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if ((temp & PIPECONF_ENABLE) == 0) {
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I915_WRITE(reg, temp | PIPECONF_ENABLE);
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POSTING_READ(reg);
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- udelay(100);
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+ intel_wait_for_vblank(dev, intel_crtc->pipe);
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}
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/* configure and enable CPU plane */
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@@ -2131,7 +2131,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
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I915_WRITE(reg, temp | TRANS_ENABLE);
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if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
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- DRM_ERROR("failed to enable transcoder\n");
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+ DRM_ERROR("failed to enable transcoder %d\n", pipe);
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intel_crtc_load_lut(crtc);
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intel_update_fbc(dev);
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@@ -2171,9 +2171,9 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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temp = I915_READ(reg);
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if (temp & PIPECONF_ENABLE) {
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I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
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+ POSTING_READ(reg);
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/* wait for cpu pipe off, pipe state */
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- if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
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- DRM_ERROR("failed to turn off cpu pipe\n");
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+ intel_wait_for_pipe_off(dev, intel_crtc->pipe);
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}
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/* Disable PF */
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