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@@ -67,6 +67,45 @@ enum {
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SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
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SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
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SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
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+
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+ SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
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+ SGE_TIMER_UPD_CIDX = 7, /* update cidx only */
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+
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+ SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
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+
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+ SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */
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+ SGE_INTRDST_IQ = 1, /* destination is an ingress queue */
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+
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+ SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */
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+ SGE_UPDATEDEL_INTR = 1, /* interrupt */
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+ SGE_UPDATEDEL_STPG = 2, /* status page */
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+ SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */
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+
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+ SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */
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+ SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */
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+ SGE_HOSTFCMODE_STPG = 2, /* sent to status page */
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+ SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */
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+
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+ SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
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+ SGE_FETCHBURSTMIN_32B = 1,
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+ SGE_FETCHBURSTMIN_64B = 2,
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+ SGE_FETCHBURSTMIN_128B = 3,
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+
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+ SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
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+ SGE_FETCHBURSTMAX_128B = 1,
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+ SGE_FETCHBURSTMAX_256B = 2,
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+ SGE_FETCHBURSTMAX_512B = 3,
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+
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+ SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
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+ SGE_CIDXFLUSHTHRESH_2 = 1,
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+ SGE_CIDXFLUSHTHRESH_4 = 2,
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+ SGE_CIDXFLUSHTHRESH_8 = 3,
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+ SGE_CIDXFLUSHTHRESH_16 = 4,
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+ SGE_CIDXFLUSHTHRESH_32 = 5,
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+ SGE_CIDXFLUSHTHRESH_64 = 6,
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+ SGE_CIDXFLUSHTHRESH_128 = 7,
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+
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+ SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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