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@@ -279,6 +279,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
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return ret;
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if (limits.vco2.maxfreq) {
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+ NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
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+ pclk, ret, pll.N1, pll.M1, pll.N2, pll.M2, pll.log2P);
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+
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reg1 = nv_rd32(dev, pll_reg + 4) & 0xff00ff00;
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reg2 = nv_rd32(dev, pll_reg + 8) & 0x8000ff00;
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nv_wr32(dev, pll_reg, 0x10000611);
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@@ -286,6 +289,9 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
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nv_wr32(dev, pll_reg + 8,
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reg2 | (pll.log2P << 28) | (pll.M2 << 16) | pll.N2);
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} else {
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+ NV_DEBUG(dev, "pclk %d out %d NM %d %d P %d\n",
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+ pclk, ret, pll.N1, pll.M1, pll.log2P);
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+
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reg1 = nv_rd32(dev, pll_reg + 4) & 0xffc00000;
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nv_wr32(dev, pll_reg, 0x50000610);
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nv_wr32(dev, pll_reg + 4, reg1 |
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