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@@ -151,7 +151,7 @@ nouveau_sgdma_unbind(struct ttm_backend *be)
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nv_wo32(gpuobj, (pte * 4) + 0, dma_offset | 3);
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nv_wo32(gpuobj, (pte * 4) + 0, dma_offset | 3);
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pte += 1;
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pte += 1;
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} else {
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} else {
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- nv_wo32(gpuobj, (pte * 4), dma_offset | 0x21);
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+ nv_wo32(gpuobj, (pte * 4) + 0, 0x00000000);
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nv_wo32(gpuobj, (pte * 4) + 4, 0x00000000);
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nv_wo32(gpuobj, (pte * 4) + 4, 0x00000000);
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pte += 2;
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pte += 2;
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}
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}
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@@ -279,9 +279,8 @@ nouveau_sgdma_init(struct drm_device *dev)
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}
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}
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} else {
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} else {
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for (i = 0; i < obj_size; i += 8) {
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for (i = 0; i < obj_size; i += 8) {
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- nv_wo32(gpuobj, i + 0,
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- dev_priv->gart_info.sg_dummy_bus | 0x21);
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- nv_wo32(gpuobj, i + 4, 0);
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+ nv_wo32(gpuobj, i + 0, 0x00000000);
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+ nv_wo32(gpuobj, i + 4, 0x00000000);
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}
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}
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}
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}
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dev_priv->engine.instmem.flush(dev);
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dev_priv->engine.instmem.flush(dev);
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