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@@ -3411,6 +3411,12 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
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IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
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}
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+ if (hw->mac.type == ixgbe_mac_82599EB) {
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+ /* DMATXCTL.EN must be set after all Tx queue config is done */
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+ dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
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+ dmatxctl |= IXGBE_DMATXCTL_TE;
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+ IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
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+ }
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for (i = 0; i < adapter->num_tx_queues; i++) {
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j = adapter->tx_ring[i]->reg_idx;
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
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@@ -3421,18 +3427,6 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
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/* enable WTHRESH=8 descriptors, to encourage burst writeback */
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txdctl |= (8 << 16);
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}
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- IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
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- }
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-
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- if (hw->mac.type == ixgbe_mac_82599EB) {
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- /* DMATXCTL.EN must be set after all Tx queue config is done */
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- dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
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- dmatxctl |= IXGBE_DMATXCTL_TE;
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- IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
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- }
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- for (i = 0; i < adapter->num_tx_queues; i++) {
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- j = adapter->tx_ring[i]->reg_idx;
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- txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
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txdctl |= IXGBE_TXDCTL_ENABLE;
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IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
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if (hw->mac.type == ixgbe_mac_82599EB) {
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