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@@ -707,11 +707,12 @@ static void rxstate(struct musb *musb, struct musb_request *req)
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fifo_count = musb_readw(epio, MUSB_RXCOUNT);
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/*
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- * use mode 1 only if we expect data of at least ep packet_sz
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- * and have not yet received a short packet
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+ * Enable Mode 1 on RX transfers only when short_not_ok flag
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+ * is set. Currently short_not_ok flag is set only from
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+ * file_storage and f_mass_storage drivers
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*/
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- if ((request->length - request->actual >= musb_ep->packet_sz) &&
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- (fifo_count >= musb_ep->packet_sz))
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+
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+ if (request->short_not_ok && fifo_count == musb_ep->packet_sz)
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use_mode_1 = 1;
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else
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use_mode_1 = 0;
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@@ -727,6 +728,27 @@ static void rxstate(struct musb *musb, struct musb_request *req)
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c = musb->dma_controller;
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channel = musb_ep->dma;
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+ /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
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+ * mode 0 only. So we do not get endpoint interrupts due to DMA
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+ * completion. We only get interrupts from DMA controller.
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+ *
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+ * We could operate in DMA mode 1 if we knew the size of the tranfer
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+ * in advance. For mass storage class, request->length = what the host
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+ * sends, so that'd work. But for pretty much everything else,
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+ * request->length is routinely more than what the host sends. For
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+ * most these gadgets, end of is signified either by a short packet,
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+ * or filling the last byte of the buffer. (Sending extra data in
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+ * that last pckate should trigger an overflow fault.) But in mode 1,
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+ * we don't get DMA completion interrupt for short packets.
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+ *
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+ * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
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+ * to get endpoint interrupt on every DMA req, but that didn't seem
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+ * to work reliably.
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+ *
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+ * REVISIT an updated g_file_storage can set req->short_not_ok, which
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+ * then becomes usable as a runtime "use mode 1" hint...
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+ */
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+
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/* Experimental: Mode1 works with mass storage use cases */
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if (use_mode_1) {
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csr |= MUSB_RXCSR_AUTOCLEAR;
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