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@@ -14,11 +14,15 @@
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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+#include <linux/clk-provider.h>
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+#include <linux/clk/mvebu.h>
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#include <linux/kexec.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/bridge-regs.h>
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+#include <linux/platform_data/usb-ehci-orion.h>
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#include <plat/irq.h>
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+#include <plat/common.h>
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#include "common.h"
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static struct of_device_id kirkwood_dt_match_table[] __initdata = {
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@@ -26,16 +30,58 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = {
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{ }
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};
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-struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
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- OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
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- OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
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- NULL),
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- OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
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- OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
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- OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
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- OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
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- {},
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-};
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+/*
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+ * There are still devices that doesn't know about DT yet. Get clock
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+ * gates here and add a clock lookup alias, so that old platform
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+ * devices still work.
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+*/
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+
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+static void __init kirkwood_legacy_clk_init(void)
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+{
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+
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+ struct device_node *np = of_find_compatible_node(
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+ NULL, NULL, "marvell,kirkwood-gating-clock");
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+
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+ struct of_phandle_args clkspec;
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+
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+ clkspec.np = np;
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+ clkspec.args_count = 1;
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+
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+ clkspec.args[0] = CGC_BIT_GE0;
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+ orion_clkdev_add(NULL, "mv643xx_eth_port.0",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_PEX0;
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+ orion_clkdev_add("0", "pcie",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_USB0;
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+ orion_clkdev_add(NULL, "orion-ehci.0",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_XOR0;
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+ orion_clkdev_add(NULL, "mv_xor_shared.0",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_XOR1;
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+ orion_clkdev_add(NULL, "mv_xor_shared.1",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_PEX1;
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+ orion_clkdev_add("1", "pcie",
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+ of_clk_get_from_provider(&clkspec));
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+
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+ clkspec.args[0] = CGC_BIT_GE1;
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+ orion_clkdev_add(NULL, "mv643xx_eth_port.1",
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+ of_clk_get_from_provider(&clkspec));
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+
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+}
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+
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+static void __init kirkwood_of_clk_init(void)
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+{
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+ mvebu_clocks_init();
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+ kirkwood_legacy_clk_init();
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+}
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static void __init kirkwood_dt_init(void)
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{
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@@ -54,7 +100,7 @@ static void __init kirkwood_dt_init(void)
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kirkwood_l2_init();
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/* Setup root of clk tree */
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- kirkwood_clk_init();
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+ kirkwood_of_clk_init();
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/* internal devices that every board has */
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kirkwood_xor0_init();
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@@ -94,8 +140,7 @@ static void __init kirkwood_dt_init(void)
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if (of_machine_is_compatible("keymile,km_kirkwood"))
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km_kirkwood_init();
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- of_platform_populate(NULL, kirkwood_dt_match_table,
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- kirkwood_auxdata_lookup, NULL);
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+ of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
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}
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static const char *kirkwood_dt_board_compat[] = {
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