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@@ -64,27 +64,39 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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mtspr SPRN_HID0,r4 /* Disable DPM */
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sync
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- /* disp-flush L1 */
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- li r4,0x4000
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- mtctr r4
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+ /* Disp-flush L1. We have a weird problem here that I never
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+ * totally figured out. On 750FX, using the ROM for the flush
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+ * results in a non-working flush. We use that workaround for
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+ * now until I finally understand what's going on. --BenH
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+ */
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+
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+ /* ROM base by default */
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lis r4,0xfff0
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-1: lwzx r0,r0,r4
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+ mfpvr r3
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+ srwi r3,r3,16
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+ cmplwi cr0,r3,0x7000
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+ bne+ 1f
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+ /* RAM base on 750FX */
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+ li r4,0
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+1: li r4,0x4000
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+ mtctr r4
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+1: lwz r0,0(r4)
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addi r4,r4,32
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bdnz 1b
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sync
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isync
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- /* disable / invalidate / enable L1 data */
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+ /* Disable / invalidate / enable L1 data */
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mfspr r3,SPRN_HID0
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- rlwinm r0,r0,0,~HID0_DCE
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+ rlwinm r3,r3,0,~(HID0_DCE | HID0_ICE)
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mtspr SPRN_HID0,r3
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sync
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isync
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- ori r3,r3,HID0_DCE|HID0_DCI
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+ ori r3,r3,(HID0_DCE|HID0_DCI|HID0_ICE|HID0_ICFI)
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sync
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isync
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mtspr SPRN_HID0,r3
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- xori r3,r3,HID0_DCI
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+ xori r3,r3,(HID0_DCI|HID0_ICFI)
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mtspr SPRN_HID0,r3
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sync
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@@ -110,11 +122,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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lis r4,2
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mtctr r4
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lis r4,0xfff0
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-1: lwzx r0,r0,r4
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+1: lwz r0,0(r4)
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+ addi r4,r4,32
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+ bdnz 1b
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+ sync
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+ isync
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+ lis r4,2
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+ mtctr r4
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+ lis r4,0xfff0
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+1: dcbf 0,r4
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addi r4,r4,32
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bdnz 1b
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sync
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isync
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+
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/* now disable L2 */
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rlwinm r5,r5,0,~L2CR_L2E
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b 2f
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@@ -135,6 +156,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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mtspr SPRN_L2CR,r4
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sync
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isync
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+
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+ /* Wait for the invalidation to complete */
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+1: mfspr r3,SPRN_L2CR
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+ rlwinm. r0,r3,0,31,31
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+ bne 1b
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+
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+ /* Clear L2I */
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xoris r4,r4,L2CR_L2I@h
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sync
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mtspr SPRN_L2CR,r4
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@@ -142,14 +170,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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/* now disable the L1 data cache */
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mfspr r0,SPRN_HID0
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- rlwinm r0,r0,0,~HID0_DCE
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+ rlwinm r0,r0,0,~(HID0_DCE|HID0_ICE)
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mtspr SPRN_HID0,r0
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sync
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isync
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/* Restore HID0[DPM] to whatever it was before */
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sync
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- mtspr SPRN_HID0,r8
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+ mfspr r0,SPRN_HID0
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+ rlwimi r0,r8,0,11,11 /* Turn back HID0[DPM] */
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+ mtspr SPRN_HID0,r0
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sync
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/* restore DR and EE */
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@@ -201,7 +231,7 @@ flush_disable_745x:
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mtctr r4
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li r4,0
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1:
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- lwzx r0,r0,r4
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+ lwz r0,0(r4)
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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isync
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