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@@ -1061,20 +1061,18 @@ int iwl_apm_init(struct iwl_priv *priv)
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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- if (priv->cfg->base_params->set_l0s) {
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- lctl = iwl_pcie_link_ctl(priv);
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- if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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- PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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- /* L1-ASPM enabled; disable(!) L0S */
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- iwl_set_bit(priv, CSR_GIO_REG,
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- CSR_GIO_REG_VAL_L0S_ENABLED);
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- IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
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- } else {
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- /* L1-ASPM disabled; enable(!) L0S */
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- iwl_clear_bit(priv, CSR_GIO_REG,
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- CSR_GIO_REG_VAL_L0S_ENABLED);
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- IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
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- }
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+ lctl = iwl_pcie_link_ctl(priv);
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+ if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
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+ PCI_CFG_LINK_CTRL_VAL_L1_EN) {
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+ /* L1-ASPM enabled; disable(!) L0S */
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+ iwl_set_bit(priv, CSR_GIO_REG,
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+ CSR_GIO_REG_VAL_L0S_ENABLED);
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+ IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
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+ } else {
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+ /* L1-ASPM disabled; enable(!) L0S */
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+ iwl_clear_bit(priv, CSR_GIO_REG,
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+ CSR_GIO_REG_VAL_L0S_ENABLED);
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+ IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
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}
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/* Configure analog phase-lock-loop before activating to D0A */
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