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@@ -491,8 +491,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
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REG_WRITE(ah, AR_DMISC(q),
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REG_WRITE(ah, AR_DMISC(q),
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AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
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AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
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- REGWRITE_BUFFER_FLUSH(ah);
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-
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if (qi->tqi_cbrPeriod) {
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if (qi->tqi_cbrPeriod) {
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REG_WRITE(ah, AR_QCBRCFG(q),
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REG_WRITE(ah, AR_QCBRCFG(q),
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SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
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SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
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@@ -508,8 +506,6 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
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AR_Q_RDYTIMECFG_EN);
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AR_Q_RDYTIMECFG_EN);
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}
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}
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- REGWRITE_BUFFER_FLUSH(ah);
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-
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REG_WRITE(ah, AR_DCHNTIME(q),
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REG_WRITE(ah, AR_DCHNTIME(q),
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SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
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SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
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(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
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(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
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