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@@ -660,6 +660,91 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
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[IRQ_DM365_EMUINT] = 7,
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};
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+/* Four Transfer Controllers on DM365 */
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+static const s8
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+dm365_queue_tc_mapping[][2] = {
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+ /* {event queue no, TC no} */
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+ {0, 0},
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+ {1, 1},
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+ {2, 2},
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+ {3, 3},
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+ {-1, -1},
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+};
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+
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+static const s8
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+dm365_queue_priority_mapping[][2] = {
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+ /* {event queue no, Priority} */
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+ {0, 7},
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+ {1, 7},
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+ {2, 7},
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+ {3, 0},
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+ {-1, -1},
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+};
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+
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+static struct edma_soc_info dm365_edma_info[] = {
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+ {
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+ .n_channel = 64,
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+ .n_region = 4,
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+ .n_slot = 256,
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+ .n_tc = 4,
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+ .n_cc = 1,
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+ .queue_tc_mapping = dm365_queue_tc_mapping,
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+ .queue_priority_mapping = dm365_queue_priority_mapping,
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+ },
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+};
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+
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+static struct resource edma_resources[] = {
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+ {
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+ .name = "edma_cc0",
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+ .start = 0x01c00000,
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+ .end = 0x01c00000 + SZ_64K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "edma_tc0",
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+ .start = 0x01c10000,
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+ .end = 0x01c10000 + SZ_1K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "edma_tc1",
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+ .start = 0x01c10400,
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+ .end = 0x01c10400 + SZ_1K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "edma_tc2",
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+ .start = 0x01c10800,
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+ .end = 0x01c10800 + SZ_1K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "edma_tc3",
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+ .start = 0x01c10c00,
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+ .end = 0x01c10c00 + SZ_1K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "edma0",
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+ .start = IRQ_CCINT0,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .name = "edma0_err",
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+ .start = IRQ_CCERRINT,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ /* not using TC*_ERR */
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+};
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+
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+static struct platform_device dm365_edma_device = {
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+ .name = "edma",
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+ .id = 0,
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+ .dev.platform_data = dm365_edma_info,
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+ .num_resources = ARRAY_SIZE(edma_resources),
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+ .resource = edma_resources,
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+};
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+
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static struct map_desc dm365_io_desc[] = {
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{
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.virtual = IO_VIRT,
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@@ -763,6 +848,8 @@ static int __init dm365_init_devices(void)
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if (!cpu_is_davinci_dm365())
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return 0;
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+ davinci_cfg_reg(DM365_INT_EDMA_CC);
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+ platform_device_register(&dm365_edma_device);
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platform_device_register(&dm365_emac_device);
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return 0;
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