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@@ -347,7 +347,7 @@ ixgb_init_hw(struct ixgb_hw *hw)
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/* Zero out the Multicast HASH table */
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DEBUGOUT("Zeroing the MTA\n");
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- for(i = 0; i < IXGB_MC_TBL_SIZE; i++)
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+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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/* Zero out the VLAN Filter Table Array */
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@@ -413,7 +413,7 @@ ixgb_init_rx_addrs(struct ixgb_hw *hw)
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/* Zero out the other 15 receive addresses. */
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DEBUGOUT("Clearing RAR[1-15]\n");
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- for(i = 1; i < IXGB_RAR_ENTRIES; i++) {
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+ for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
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/* Write high reg first to disable the AV bit first */
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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@@ -452,19 +452,18 @@ ixgb_mc_addr_list_update(struct ixgb_hw *hw,
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/* Clear RAR[1-15] */
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DEBUGOUT(" Clearing RAR[1-15]\n");
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- for(i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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+ for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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}
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/* Clear the MTA */
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DEBUGOUT(" Clearing MTA\n");
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- for(i = 0; i < IXGB_MC_TBL_SIZE; i++) {
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+ for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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- }
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/* Add the new addresses */
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- for(i = 0; i < mc_addr_count; i++) {
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+ for (i = 0; i < mc_addr_count; i++) {
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DEBUGOUT(" Adding the multicast addresses:\n");
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DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
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mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)],
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@@ -649,7 +648,7 @@ ixgb_clear_vfta(struct ixgb_hw *hw)
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{
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u32 offset;
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- for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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+ for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
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IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
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return;
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}
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@@ -790,7 +789,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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- for(i = 0; i < 10; i++)
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+ for (i = 0; i < 10; i++)
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{
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udelay(10);
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@@ -817,7 +816,7 @@ ixgb_read_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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- for(i = 0; i < 10; i++)
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+ for (i = 0; i < 10; i++)
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{
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udelay(10);
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@@ -886,7 +885,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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- for(i = 0; i < 10; i++)
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+ for (i = 0; i < 10; i++)
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{
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udelay(10);
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@@ -913,7 +912,7 @@ ixgb_write_phy_reg(struct ixgb_hw *hw,
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** from the CPU Write to the Ready bit assertion.
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**************************************************************/
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- for(i = 0; i < 10; i++)
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+ for (i = 0; i < 10; i++)
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{
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udelay(10);
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