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@@ -45,24 +45,29 @@
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#define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
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#define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
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#define MPC10X_UART0_IRQ (EPIC_IRQ_BASE + 4 + NUM_8259_INTERRUPTS)
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+#define MPC10X_UART1_IRQ (EPIC_IRQ_BASE + 5 + NUM_8259_INTERRUPTS)
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#else
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#define MPC10X_I2C_IRQ -1
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#define MPC10X_DMA0_IRQ -1
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#define MPC10X_DMA1_IRQ -1
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#define MPC10X_UART0_IRQ -1
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+#define MPC10X_UART1_IRQ -1
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#endif
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static struct fsl_i2c_platform_data mpc10x_i2c_pdata = {
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.device_flags = 0,
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};
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-static struct plat_serial8250_port serial_platform_data[] = {
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+static struct plat_serial8250_port serial_plat_uart0[] = {
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[0] = {
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.mapbase = 0x4500,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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- [1] = {
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+ { },
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+};
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+static struct plat_serial8250_port serial_plat_uart1[] = {
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+ [0] = {
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.mapbase = 0x4600,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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@@ -133,11 +138,17 @@ struct platform_device ppc_sys_platform_devices[] = {
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},
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},
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},
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- [MPC10X_DUART] = {
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+ [MPC10X_UART0] = {
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.name = "serial8250",
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.id = 0,
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- .dev.platform_data = serial_platform_data,
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+ .dev.platform_data = serial_plat_uart0,
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},
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+ [MPC10X_UART1] = {
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+ .name = "serial8250",
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+ .id = 1,
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+ .dev.platform_data = serial_plat_uart1,
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+ },
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+
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};
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/* We use the PCI ID to match on */
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@@ -147,10 +158,10 @@ struct ppc_sys_spec ppc_sys_specs[] = {
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.ppc_sys_name = "8245",
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.mask = 0xFFFFFFFF,
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.value = MPC10X_BRIDGE_8245,
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- .num_devices = 4,
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+ .num_devices = 5,
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.device_list = (enum ppc_sys_devices[])
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{
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- MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_DUART,
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+ MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, MPC10X_UART0, MPC10X_UART1,
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},
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},
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{
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@@ -180,6 +191,25 @@ struct ppc_sys_spec ppc_sys_specs[] = {
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},
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};
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+/*
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+ * mach_mpc10x_fixup: This function enables DUART mode if it detects
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+ * if it detects two UARTS in the platform device entries.
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+ */
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+static int __init mach_mpc10x_fixup(struct platform_device *pdev)
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+{
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+ if (strncmp (pdev->name, "serial8250", 10) == 0 && pdev->id == 1)
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+ writeb(readb(serial_plat_uart1[0].membase + 0x11) | 0x1,
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+ serial_plat_uart1[0].membase + 0x11);
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+ return 0;
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+}
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+
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+static int __init mach_mpc10x_init(void)
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+{
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+ ppc_sys_device_fixup = mach_mpc10x_fixup;
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+ return 0;
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+}
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+postcore_initcall(mach_mpc10x_init);
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+
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/* Set resources to match bridge memory map */
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void __init
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mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
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@@ -219,6 +249,7 @@ mpc10x_bridge_set_resources(int map, struct pci_controller *hose)
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ppc_md.progress("mpc10x:exit1", 0x100);
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}
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}
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+
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/*
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* Do some initialization and put the EUMB registers at the specified address
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* (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
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@@ -411,11 +442,13 @@ mpc10x_bridge_init(struct pci_controller *hose,
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ppc_sys_platform_devices[MPC10X_DMA1].resource[1].start = MPC10X_DMA1_IRQ;
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ppc_sys_platform_devices[MPC10X_DMA1].resource[1].end = MPC10X_DMA1_IRQ;
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- serial_platform_data[0].mapbase += phys_eumb_base;
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- serial_platform_data[0].irq = MPC10X_UART0_IRQ;
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+ serial_plat_uart0[0].mapbase += phys_eumb_base;
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+ serial_plat_uart0[0].irq = MPC10X_UART0_IRQ;
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+ serial_plat_uart0[0].membase = ioremap(serial_plat_uart0[0].mapbase, 0x100);
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- serial_platform_data[1].mapbase += phys_eumb_base;
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- serial_platform_data[1].irq = MPC10X_UART0_IRQ + 1;
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+ serial_plat_uart1[0].mapbase += phys_eumb_base;
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+ serial_plat_uart1[0].irq = MPC10X_UART1_IRQ;
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+ serial_plat_uart1[0].membase = ioremap(serial_plat_uart1[0].mapbase, 0x100);
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/*
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* 8240 erratum 26, 8241/8245 erratum 29, 107 erratum 23: speculative
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