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@@ -842,7 +842,7 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
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static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
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{
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- if (AR_SREV_9287_11(ah))
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+ if (AR_SREV_9287_11_OR_LATER(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9287Modes_rx_gain_9287_1_1,
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ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
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@@ -853,7 +853,7 @@ static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
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else if (AR_SREV_9280_20(ah))
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ath9k_hw_init_rxgain_ini(ah);
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- if (AR_SREV_9287_11(ah)) {
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+ if (AR_SREV_9287_11_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9287Modes_tx_gain_9287_1_1,
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ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
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@@ -965,7 +965,7 @@ int ath9k_hw_init(struct ath_hw *ah)
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ath9k_hw_init_mode_regs(ah);
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if (ah->is_pciexpress)
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- ath9k_hw_configpcipowersave(ah, 0);
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+ ath9k_hw_configpcipowersave(ah, 0, 0);
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else
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ath9k_hw_disablepcie(ah);
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@@ -1273,6 +1273,15 @@ static void ath9k_hw_override_ini(struct ath_hw *ah,
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*/
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REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
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+ if (AR_SREV_9280_10_OR_LATER(ah)) {
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+ val = REG_READ(ah, AR_PCU_MISC_MODE2) &
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+ (~AR_PCU_MISC_MODE2_HWWAR1);
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+
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+ if (AR_SREV_9287_10_OR_LATER(ah))
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+ val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
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+
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+ REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
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+ }
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if (!AR_SREV_5416_20_OR_LATER(ah) ||
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AR_SREV_9280_10_OR_LATER(ah))
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@@ -1784,7 +1793,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
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static bool ath9k_hw_chip_reset(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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- if (OLC_FOR_AR9280_20_LATER) {
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+ if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
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if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
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return false;
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} else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
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@@ -2338,6 +2347,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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struct ath9k_channel *curchan = ah->curchan;
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u32 saveDefAntenna;
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u32 macStaId1;
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+ u64 tsf = 0;
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int i, rx_chainmask, r;
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ah->extprotspacing = sc->ht_extprotspacing;
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@@ -2347,7 +2357,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
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return -EIO;
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- if (curchan)
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+ if (curchan && !ah->chip_fullsleep)
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ath9k_hw_getnf(ah, curchan);
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if (bChannelChange &&
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@@ -2356,8 +2366,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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(chan->channel != ah->curchan->channel) &&
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((chan->channelFlags & CHANNEL_ALL) ==
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(ah->curchan->channelFlags & CHANNEL_ALL)) &&
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- (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
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- !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
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+ !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
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+ IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
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if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
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ath9k_hw_loadnf(ah, ah->curchan);
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@@ -2372,6 +2382,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
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+ /* For chips on which RTC reset is done, save TSF before it gets cleared */
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+ if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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+ tsf = ath9k_hw_gettsf64(ah);
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+
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saveLedState = REG_READ(ah, AR_CFG_LED) &
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(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
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AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
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@@ -2398,6 +2412,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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udelay(50);
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}
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+ /* Restore TSF */
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+ if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
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+ ath9k_hw_settsf64(ah, tsf);
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+
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if (AR_SREV_9280_10_OR_LATER(ah))
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
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@@ -3005,9 +3023,10 @@ void ath9k_ps_restore(struct ath_softc *sc)
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* Programming the SerDes must go through the same 288 bit serial shift
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* register as the other analog registers. Hence the 9 writes.
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*/
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-void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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+void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
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{
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u8 i;
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+ u32 val;
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if (ah->is_pciexpress != true)
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return;
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@@ -3017,84 +3036,113 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
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return;
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/* Nothing to do on restore for 11N */
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- if (restore)
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- return;
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+ if (!restore) {
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+ if (AR_SREV_9280_20_OR_LATER(ah)) {
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+ /*
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+ * AR9280 2.0 or later chips use SerDes values from the
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+ * initvals.h initialized depending on chipset during
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+ * ath9k_hw_init()
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+ */
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+ for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
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+ REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
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+ INI_RA(&ah->iniPcieSerdes, i, 1));
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+ }
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+ } else if (AR_SREV_9280(ah) &&
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+ (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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+
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+ /* RX shut off when elecidle is asserted */
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
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+
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+ /* Shut off CLKREQ active in L1 */
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+ if (ah->config.pcie_clock_req)
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
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+ else
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
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- if (AR_SREV_9280_20_OR_LATER(ah)) {
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- /*
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- * AR9280 2.0 or later chips use SerDes values from the
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- * initvals.h initialized depending on chipset during
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- * ath9k_hw_init()
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- */
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- for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
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- REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
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- INI_RA(&ah->iniPcieSerdes, i, 1));
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- }
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- } else if (AR_SREV_9280(ah) &&
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- (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
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- /* RX shut off when elecidle is asserted */
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- REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
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+ /* Load the new settings */
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+ REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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- /* Shut off CLKREQ active in L1 */
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- if (ah->config.pcie_clock_req)
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
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- else
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
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-
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
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+ } else {
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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- /* Load the new settings */
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- REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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+ /* RX shut off when elecidle is asserted */
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
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- } else {
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
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+ /*
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+ * Ignore ah->ah_config.pcie_clock_req setting for
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+ * pre-AR9280 11n
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+ */
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
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- /* RX shut off when elecidle is asserted */
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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+ REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
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- /*
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- * Ignore ah->ah_config.pcie_clock_req setting for
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- * pre-AR9280 11n
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- */
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
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+ /* Load the new settings */
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+ REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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+ }
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
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- REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
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+ udelay(1000);
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- /* Load the new settings */
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- REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
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- }
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+ /* set bit 19 to allow forcing of pcie core into L1 state */
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+ REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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- udelay(1000);
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+ /* Several PCIe massages to ensure proper behaviour */
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+ if (ah->config.pcie_waen) {
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+ val = ah->config.pcie_waen;
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+ if (!power_off)
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+ val &= (~AR_WA_D3_L1_DISABLE);
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+ } else {
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+ if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
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+ AR_SREV_9287(ah)) {
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+ val = AR9285_WA_DEFAULT;
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+ if (!power_off)
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+ val &= (~AR_WA_D3_L1_DISABLE);
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+ } else if (AR_SREV_9280(ah)) {
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+ /*
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+ * On AR9280 chips bit 22 of 0x4004 needs to be
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+ * set otherwise card may disappear.
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+ */
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+ val = AR9280_WA_DEFAULT;
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+ if (!power_off)
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+ val &= (~AR_WA_D3_L1_DISABLE);
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+ } else
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+ val = AR_WA_DEFAULT;
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+ }
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- /* set bit 19 to allow forcing of pcie core into L1 state */
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- REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
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+ REG_WRITE(ah, AR_WA, val);
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+ }
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- /* Several PCIe massages to ensure proper behaviour */
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- if (ah->config.pcie_waen) {
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- REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
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- } else {
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- if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
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- REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
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+ if (power_off) {
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/*
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- * On AR9280 chips bit 22 of 0x4004 needs to be set to
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- * otherwise card may disappear.
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+ * Set PCIe workaround bits
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+ * bit 14 in WA register (disable L1) should only
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+ * be set when device enters D3 and be cleared
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+ * when device comes back to D0.
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*/
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- else if (AR_SREV_9280(ah))
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- REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
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- else
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- REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
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+ if (ah->config.pcie_waen) {
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+ if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
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+ REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
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+ } else {
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+ if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
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+ AR_SREV_9287(ah)) &&
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+ (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
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+ (AR_SREV_9280(ah) &&
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+ (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
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+ REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
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+ }
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+ }
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}
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}
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@@ -3652,15 +3700,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
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}
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#endif
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- if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
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- (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
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- (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
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- (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
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- (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
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- (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
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- pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
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- else
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- pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
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+ pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
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if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
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pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
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