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@@ -2597,7 +2597,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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- u32 reg, temp, i;
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+ u32 reg, temp, i, j;
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/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
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for train result */
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@@ -2613,97 +2613,99 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
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DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
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I915_READ(FDI_RX_IIR(pipe)));
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- /* enable CPU FDI TX and PCH FDI RX */
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- reg = FDI_TX_CTL(pipe);
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- temp = I915_READ(reg);
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- temp &= ~FDI_DP_PORT_WIDTH_MASK;
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- temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
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- temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
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- temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
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- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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- temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
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- temp |= FDI_COMPOSITE_SYNC;
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- I915_WRITE(reg, temp | FDI_TX_ENABLE);
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-
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- I915_WRITE(FDI_RX_MISC(pipe),
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- FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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-
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- reg = FDI_RX_CTL(pipe);
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- temp = I915_READ(reg);
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- temp &= ~FDI_LINK_TRAIN_AUTO;
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- temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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- temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
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- temp |= FDI_COMPOSITE_SYNC;
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- I915_WRITE(reg, temp | FDI_RX_ENABLE);
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+ /* Try each vswing and preemphasis setting twice before moving on */
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+ for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
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+ /* disable first in case we need to retry */
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+ reg = FDI_TX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
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+ temp &= ~FDI_TX_ENABLE;
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+ I915_WRITE(reg, temp);
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- POSTING_READ(reg);
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- udelay(150);
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+ reg = FDI_RX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ temp &= ~FDI_LINK_TRAIN_AUTO;
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+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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+ temp &= ~FDI_RX_ENABLE;
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+ I915_WRITE(reg, temp);
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- for (i = 0; i < 4; i++) {
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+ /* enable CPU FDI TX and PCH FDI RX */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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+ temp &= ~FDI_DP_PORT_WIDTH_MASK;
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+ temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
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+ temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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- temp |= snb_b_fdi_train_param[i];
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- I915_WRITE(reg, temp);
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+ temp |= snb_b_fdi_train_param[j/2];
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+ temp |= FDI_COMPOSITE_SYNC;
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+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
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- POSTING_READ(reg);
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- udelay(500);
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+ I915_WRITE(FDI_RX_MISC(pipe),
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+ FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
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- reg = FDI_RX_IIR(pipe);
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+ reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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- DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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-
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- if (temp & FDI_RX_BIT_LOCK ||
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- (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
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- I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
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- DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
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- break;
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- }
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- }
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- if (i == 4)
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- DRM_ERROR("FDI train 1 fail!\n");
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+ temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
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+ temp |= FDI_COMPOSITE_SYNC;
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+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
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- /* Train 2 */
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- reg = FDI_TX_CTL(pipe);
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- temp = I915_READ(reg);
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- temp &= ~FDI_LINK_TRAIN_NONE_IVB;
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- temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
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- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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- temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
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- I915_WRITE(reg, temp);
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+ POSTING_READ(reg);
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+ udelay(1); /* should be 0.5us */
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- reg = FDI_RX_CTL(pipe);
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- temp = I915_READ(reg);
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- temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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- temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
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- I915_WRITE(reg, temp);
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+ for (i = 0; i < 4; i++) {
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+ reg = FDI_RX_IIR(pipe);
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+ temp = I915_READ(reg);
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+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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- POSTING_READ(reg);
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- udelay(150);
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+ if (temp & FDI_RX_BIT_LOCK ||
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+ (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
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+ I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
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+ DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
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+ i);
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+ break;
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+ }
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+ udelay(1); /* should be 0.5us */
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+ }
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+ if (i == 4) {
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+ DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
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+ continue;
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+ }
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- for (i = 0; i < 4; i++) {
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+ /* Train 2 */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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- temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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- temp |= snb_b_fdi_train_param[i];
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+ temp &= ~FDI_LINK_TRAIN_NONE_IVB;
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+ temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
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+ I915_WRITE(reg, temp);
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+
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+ reg = FDI_RX_CTL(pipe);
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+ temp = I915_READ(reg);
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+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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+ temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
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I915_WRITE(reg, temp);
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POSTING_READ(reg);
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- udelay(500);
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+ udelay(2); /* should be 1.5us */
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- reg = FDI_RX_IIR(pipe);
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- temp = I915_READ(reg);
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- DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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+ for (i = 0; i < 4; i++) {
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+ reg = FDI_RX_IIR(pipe);
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+ temp = I915_READ(reg);
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+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
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- if (temp & FDI_RX_SYMBOL_LOCK) {
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- I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
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- DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
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- break;
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+ if (temp & FDI_RX_SYMBOL_LOCK ||
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+ (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
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+ I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
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+ DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
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+ i);
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+ goto train_done;
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+ }
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+ udelay(2); /* should be 1.5us */
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}
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+ if (i == 4)
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+ DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
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}
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- if (i == 4)
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- DRM_ERROR("FDI train 2 fail!\n");
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+train_done:
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DRM_DEBUG_KMS("FDI train done.\n");
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}
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