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@@ -3,20 +3,8 @@
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*/
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/*
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- * This assumes you have a 7.272727 MHz clock for your UART.
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- * The documentation implies a 40Mhz clock, and elsewhere a 7Mhz clock
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- * Clarified: 7.2727MHz on LASI. Not yet clarified for DINO
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+ * This is used for 16550-compatible UARTs
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*/
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+#define BASE_BAUD ( 1843200 / 16 )
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-#define LASI_BASE_BAUD ( 7272727 / 16 )
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-#define BASE_BAUD LASI_BASE_BAUD
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-
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-/*
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- * We don't use the ISA probing code, so these entries are just to reserve
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- * space. Some example (maximal) configurations:
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- * - 712 w/ additional Lasi & RJ16 ports: 4
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- * - J5k w/ PCI serial cards: 2 + 4 * card ~= 34
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- * A500 w/ PCI serial cards: 5 + 4 * card ~= 17
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- */
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-
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#define SERIAL_PORT_DFNS
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