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@@ -235,17 +235,16 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
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while (*wb_comp != DMAE_COMP_VAL) {
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DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
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- /* adjust delay for emulation/FPGA */
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- if (CHIP_REV_IS_SLOW(bp))
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- msleep(100);
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- else
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- udelay(5);
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-
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if (!cnt) {
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BNX2X_ERR("dmae timeout!\n");
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break;
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}
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cnt--;
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+ /* adjust delay for emulation/FPGA */
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+ if (CHIP_REV_IS_SLOW(bp))
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+ msleep(100);
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+ else
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+ udelay(5);
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}
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mutex_unlock(&bp->dmae_mutex);
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@@ -308,17 +307,16 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
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while (*wb_comp != DMAE_COMP_VAL) {
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- /* adjust delay for emulation/FPGA */
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- if (CHIP_REV_IS_SLOW(bp))
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- msleep(100);
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- else
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- udelay(5);
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-
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if (!cnt) {
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BNX2X_ERR("dmae timeout!\n");
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break;
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}
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cnt--;
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+ /* adjust delay for emulation/FPGA */
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+ if (CHIP_REV_IS_SLOW(bp))
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+ msleep(100);
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+ else
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+ udelay(5);
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}
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DP(BNX2X_MSG_OFF, "data [0x%08x 0x%08x 0x%08x 0x%08x]\n",
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bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
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@@ -3094,12 +3092,12 @@ static int bnx2x_stats_comp(struct bnx2x *bp)
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might_sleep();
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while (*stats_comp != DMAE_COMP_VAL) {
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- msleep(1);
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if (!cnt) {
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BNX2X_ERR("timeout waiting for stats finished\n");
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break;
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}
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cnt--;
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+ msleep(1);
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}
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return 1;
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}
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@@ -6483,7 +6481,6 @@ static int bnx2x_stop_leading(struct bnx2x *bp)
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so there is not much to do if this times out
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*/
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while (dsb_sp_prod_idx == *bp->dsb_sp_prod) {
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- msleep(1);
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if (!cnt) {
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DP(NETIF_MSG_IFDOWN, "timeout waiting for port del "
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"dsb_sp_prod 0x%x != dsb_sp_prod_idx 0x%x\n",
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