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@@ -27,6 +27,7 @@
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#include <linux/limits.h>
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#include <linux/bitops.h>
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+#include <mach/cpu.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include <asm/div64.h>
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@@ -1067,17 +1068,17 @@ static int __init omap2_clk_arch_init(void)
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return -EINVAL;
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/* REVISIT: not yet ready for 343x */
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-#if 0
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- if (clk_set_rate(&virt_prcm_set, mpurate))
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- printk(KERN_ERR "Could not find matching MPU rate\n");
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-#endif
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+ if (clk_set_rate(&dpll1_ck, mpurate))
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+ printk(KERN_ERR "*** Unable to set MPU rate\n");
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recalculate_root_clocks();
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- printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
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+ printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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- (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
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- (core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
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+ (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
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+ (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
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+
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+ calibrate_delay();
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return 0;
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}
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@@ -1136,7 +1137,7 @@ int __init omap2_clk_init(void)
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recalculate_root_clocks();
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- printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
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+ printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
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(core_ck.rate / 1000000), (arm_fck.rate / 1000000));
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