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@@ -929,9 +929,6 @@ int __init pcibios_init(void)
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struct pci_controller *controller = &pci_controllers[i];
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gxio_trio_context_t *trio_context = controller->trio;
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struct pci_bus *root_bus = pci_controllers[i].root_bus;
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- struct pci_bus *next_bus;
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- uint32_t bus_address_hi;
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- struct pci_dev *dev;
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int ret;
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int j;
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@@ -945,35 +942,6 @@ int __init pcibios_init(void)
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/* Configure the max_payload_size values for this domain. */
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fixup_read_and_payload_sizes(controller);
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- list_for_each_entry(dev, &root_bus->devices, bus_list) {
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- /* Find the PCI host controller, ie. the 1st bridge. */
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- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
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- (PCI_SLOT(dev->devfn) == 0)) {
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- next_bus = dev->subordinate;
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- pci_controllers[i].mem_resources[0] =
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- *next_bus->resource[0];
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- pci_controllers[i].mem_resources[1] =
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- *next_bus->resource[1];
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- pci_controllers[i].mem_resources[2] =
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- *next_bus->resource[2];
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-
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- break;
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- }
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- }
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-
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- if (pci_controllers[i].mem_resources[1].flags & IORESOURCE_MEM)
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- bus_address_hi =
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- pci_controllers[i].mem_resources[1].start >> 32;
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- else if (pci_controllers[i].mem_resources[2].flags & IORESOURCE_PREFETCH)
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- bus_address_hi =
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- pci_controllers[i].mem_resources[2].start >> 32;
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- else {
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- /* This is unlikely. */
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- pr_err("PCI: no memory resources on TRIO %d mac %d\n",
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- controller->trio_index, controller->mac);
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- continue;
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- }
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-
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/*
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* Alloc a PIO region for PCI memory access for each RC port.
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*/
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@@ -1153,16 +1121,13 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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resource_size_t start;
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resource_size_t end;
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int trio_fd;
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- int i, j;
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+ int i;
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start = phys_addr;
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end = phys_addr + size - 1;
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/*
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- * In the following, each PCI controller's mem_resources[1]
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- * represents its (non-prefetchable) PCI memory resource and
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- * mem_resources[2] refers to its prefetchable PCI memory resource.
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- * By searching phys_addr in each controller's mem_resources[], we can
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+ * By searching phys_addr in each controller's mem_space, we can
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* determine the controller that should accept the PCI memory access.
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*/
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@@ -1174,25 +1139,18 @@ void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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if (pci_controllers[i].root_bus == NULL)
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continue;
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- for (j = 1; j < 3; j++) {
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- bar_start =
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- pci_controllers[i].mem_resources[j].start;
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- bar_end =
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- pci_controllers[i].mem_resources[j].end;
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-
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- if ((start >= bar_start) && (end <= bar_end)) {
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+ bar_start = pci_controllers[i].mem_space.start;
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+ bar_end = pci_controllers[i].mem_space.end;
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- controller = &pci_controllers[i];
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-
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- goto got_it;
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- }
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+ if ((start >= bar_start) && (end <= bar_end)) {
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+ controller = &pci_controllers[i];
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+ break;
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}
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}
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if (controller == NULL)
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return NULL;
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-got_it:
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trio_fd = controller->trio->fd;
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/* Convert the resource start to the bus address offset. */
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@@ -1225,10 +1183,8 @@ void __iomem *ioport_map(unsigned long port, unsigned int size)
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end = port + size - 1;
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/*
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- * In the following, each PCI controller's mem_resources[0]
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- * represents its PCI I/O resource. By searching port in each
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- * controller's mem_resources[0], we can determine the controller
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- * that should accept the PCI I/O access.
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+ * By searching the port in each controller's io_space, we can
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+ * determine the controller that should accept the PCI I/O access.
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*/
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for (i = 0; i < num_rc_controllers; i++) {
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@@ -1239,21 +1195,18 @@ void __iomem *ioport_map(unsigned long port, unsigned int size)
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if (pci_controllers[i].root_bus == NULL)
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continue;
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- bar_start = pci_controllers[i].mem_resources[0].start;
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- bar_end = pci_controllers[i].mem_resources[0].end;
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+ bar_start = pci_controllers[i].io_space.start;
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+ bar_end = pci_controllers[i].io_space.end;
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if ((start >= bar_start) && (end <= bar_end)) {
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-
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controller = &pci_controllers[i];
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-
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- goto got_it;
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+ break;
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}
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}
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if (controller == NULL)
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return NULL;
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-got_it:
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trio_fd = controller->trio->fd;
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/* Convert the resource start to the bus address offset. */
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