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@@ -43,7 +43,8 @@ struct mt312_state {
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struct dvb_frontend frontend;
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u8 id;
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- u8 frequency;
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+ unsigned long xtal;
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+ u8 freq_mult;
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};
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static int debug;
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@@ -53,8 +54,6 @@ static int debug;
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printk(KERN_DEBUG "mt312: " args); \
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} while (0)
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-#define MT312_SYS_CLK 90000000UL /* 90 MHz */
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-#define MT312_LPOWER_SYS_CLK 60000000UL /* 60 MHz */
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#define MT312_PLL_CLK 10000000UL /* 10 MHz */
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static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
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@@ -209,7 +208,7 @@ static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
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dprintk("sym_rat_op=%d dec_ratio=%d\n",
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sym_rat_op, dec_ratio);
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dprintk("*sr(manual) = %lu\n",
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- (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
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+ (((state->xtal * 8192) / (sym_rat_op + 8192)) *
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2) - dec_ratio);
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}
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@@ -242,7 +241,7 @@ static int mt312_initfe(struct dvb_frontend *fe)
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/* wake up */
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ret = mt312_writereg(state, CONFIG,
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- (state->frequency == 60 ? 0x88 : 0x8c));
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+ (state->freq_mult == 6 ? 0x88 : 0x8c));
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if (ret < 0)
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return ret;
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@@ -266,11 +265,10 @@ static int mt312_initfe(struct dvb_frontend *fe)
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}
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/* SYS_CLK */
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- buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK :
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- MT312_SYS_CLK) * 2, 1000000);
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+ buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
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/* DISEQC_RATIO */
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- buf[1] = mt312_div(MT312_PLL_CLK, 22000 * 4);
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+ buf[1] = mt312_div(state->xtal, 22000 * 4);
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ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
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if (ret < 0)
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@@ -535,17 +533,17 @@ static int mt312_set_frontend(struct dvb_frontend *fe,
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return ret;
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if (p->u.qpsk.symbol_rate >= 30000000) {
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/* Note that 30MS/s should use 90MHz */
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- if ((config_val & 0x0c) == 0x08) {
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+ if (state->freq_mult == 6) {
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/* We are running 60MHz */
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- state->frequency = 90;
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+ state->freq_mult = 9;
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ret = mt312_initfe(fe);
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if (ret < 0)
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return ret;
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}
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} else {
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- if ((config_val & 0x0c) == 0x0C) {
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+ if (state->freq_mult == 9) {
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/* We are running 90MHz */
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- state->frequency = 60;
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+ state->freq_mult = 6;
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ret = mt312_initfe(fe);
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if (ret < 0)
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return ret;
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@@ -664,6 +662,7 @@ static void mt312_release(struct dvb_frontend *fe)
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kfree(state);
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}
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+#define MT312_SYS_CLK 90000000UL /* 90 MHz */
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static struct dvb_frontend_ops vp310_mt312_ops = {
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.info = {
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@@ -671,8 +670,8 @@ static struct dvb_frontend_ops vp310_mt312_ops = {
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.type = FE_QPSK,
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.frequency_min = 950000,
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.frequency_max = 2150000,
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- .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
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- .symbol_rate_min = MT312_SYS_CLK / 128,
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+ .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128, /* FIXME: adjust freq to real used xtal */
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+ .symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
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.symbol_rate_max = MT312_SYS_CLK / 2,
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.caps =
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FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
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@@ -729,11 +728,13 @@ struct dvb_frontend *vp310_mt312_attach(const struct mt312_config *config,
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switch (state->id) {
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case ID_VP310:
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strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
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- state->frequency = 90;
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+ state->xtal = MT312_PLL_CLK;
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+ state->freq_mult = 9;
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break;
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case ID_MT312:
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strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
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- state->frequency = 60;
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+ state->xtal = MT312_PLL_CLK;
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+ state->freq_mult = 6;
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break;
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default:
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printk(KERN_WARNING "Only Zarlink VP310/MT312"
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