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+===========================================
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+ARM topology binding description
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+===========================================
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+
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+===========================================
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+1 - Introduction
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+===========================================
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+
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+In an ARM system, the hierarchy of CPUs is defined through three entities that
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+are used to describe the layout of physical CPUs in the system:
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+
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+- cluster
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+- core
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+- thread
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+
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+The cpu nodes (bindings defined in [1]) represent the devices that
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+correspond to physical CPUs and are to be mapped to the hierarchy levels.
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+
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+The bottom hierarchy level sits at core or thread level depending on whether
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+symmetric multi-threading (SMT) is supported or not.
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+
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+For instance in a system where CPUs support SMT, "cpu" nodes represent all
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+threads existing in the system and map to the hierarchy level "thread" above.
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+In systems where SMT is not supported "cpu" nodes represent all cores present
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+in the system and map to the hierarchy level "core" above.
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+
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+ARM topology bindings allow one to associate cpu nodes with hierarchical groups
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+corresponding to the system hierarchy; syntactically they are defined as device
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+tree nodes.
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+
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+The remainder of this document provides the topology bindings for ARM, based
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+on the ePAPR standard, available from:
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+
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+http://www.power.org/documentation/epapr-version-1-1/
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+
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+If not stated otherwise, whenever a reference to a cpu node phandle is made its
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+value must point to a cpu node compliant with the cpu node bindings as
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+documented in [1].
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+A topology description containing phandles to cpu nodes that are not compliant
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+with bindings standardized in [1] is therefore considered invalid.
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+
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+===========================================
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+2 - cpu-map node
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+===========================================
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+
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+The ARM CPU topology is defined within the cpu-map node, which is a direct
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+child of the cpus node and provides a container where the actual topology
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+nodes are listed.
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+
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+- cpu-map node
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+
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+ Usage: Optional - On ARM SMP systems provide CPUs topology to the OS.
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+ ARM uniprocessor systems do not require a topology
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+ description and therefore should not define a
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+ cpu-map node.
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+
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+ Description: The cpu-map node is just a container node where its
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+ subnodes describe the CPU topology.
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+
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+ Node name must be "cpu-map".
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+
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+ The cpu-map node's parent node must be the cpus node.
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+
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+ The cpu-map node's child nodes can be:
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+
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+ - one or more cluster nodes
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+
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+ Any other configuration is considered invalid.
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+
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+The cpu-map node can only contain three types of child nodes:
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+
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+- cluster node
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+- core node
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+- thread node
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+
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+whose bindings are described in paragraph 3.
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+
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+The nodes describing the CPU topology (cluster/core/thread) can only be
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+defined within the cpu-map node.
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+Any other configuration is consider invalid and therefore must be ignored.
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+
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+===========================================
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+2.1 - cpu-map child nodes naming convention
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+===========================================
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+
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+cpu-map child nodes must follow a naming convention where the node name
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+must be "clusterN", "coreN", "threadN" depending on the node type (ie
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+cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes which
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+are siblings within a single common parent node must be given a unique and
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+sequential N value, starting from 0).
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+cpu-map child nodes which do not share a common parent node can have the same
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+name (ie same number N as other cpu-map child nodes at different device tree
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+levels) since name uniqueness will be guaranteed by the device tree hierarchy.
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+
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+===========================================
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+3 - cluster/core/thread node bindings
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+===========================================
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+
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+Bindings for cluster/cpu/thread nodes are defined as follows:
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+
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+- cluster node
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+
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+ Description: must be declared within a cpu-map node, one node
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+ per cluster. A system can contain several layers of
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+ clustering and cluster nodes can be contained in parent
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+ cluster nodes.
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+
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+ The cluster node name must be "clusterN" as described in 2.1 above.
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+ A cluster node can not be a leaf node.
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+
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+ A cluster node's child nodes must be:
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+
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+ - one or more cluster nodes; or
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+ - one or more core nodes
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+
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+ Any other configuration is considered invalid.
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+
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+- core node
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+
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+ Description: must be declared in a cluster node, one node per core in
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+ the cluster. If the system does not support SMT, core
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+ nodes are leaf nodes, otherwise they become containers of
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+ thread nodes.
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+
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+ The core node name must be "coreN" as described in 2.1 above.
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+
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+ A core node must be a leaf node if SMT is not supported.
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+
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+ Properties for core nodes that are leaf nodes:
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+
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+ - cpu
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+ Usage: required
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+ Value type: <phandle>
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+ Definition: a phandle to the cpu node that corresponds to the
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+ core node.
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+
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+ If a core node is not a leaf node (CPUs supporting SMT) a core node's
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+ child nodes can be:
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+
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+ - one or more thread nodes
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+
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+ Any other configuration is considered invalid.
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+
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+- thread node
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+
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+ Description: must be declared in a core node, one node per thread
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+ in the core if the system supports SMT. Thread nodes are
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+ always leaf nodes in the device tree.
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+
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+ The thread node name must be "threadN" as described in 2.1 above.
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+
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+ A thread node must be a leaf node.
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+
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+ A thread node must contain the following property:
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+
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+ - cpu
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+ Usage: required
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+ Value type: <phandle>
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+ Definition: a phandle to the cpu node that corresponds to
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+ the thread node.
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+
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+===========================================
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+4 - Example dts
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+===========================================
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+
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+Example 1 (ARM 64-bit, 16-cpu system, two clusters of clusters):
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+
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+cpus {
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+ #size-cells = <0>;
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+ #address-cells = <2>;
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+
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+ cpu-map {
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+ cluster0 {
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+ cluster0 {
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+ core0 {
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+ thread0 {
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+ cpu = <&CPU0>;
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+ };
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+ thread1 {
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+ cpu = <&CPU1>;
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+ };
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+ };
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+
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+ core1 {
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+ thread0 {
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+ cpu = <&CPU2>;
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+ };
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+ thread1 {
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+ cpu = <&CPU3>;
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+ };
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+ };
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+ };
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+
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+ cluster1 {
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+ core0 {
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+ thread0 {
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+ cpu = <&CPU4>;
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+ };
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+ thread1 {
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+ cpu = <&CPU5>;
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+ };
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+ };
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+
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+ core1 {
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+ thread0 {
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+ cpu = <&CPU6>;
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+ };
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+ thread1 {
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+ cpu = <&CPU7>;
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+ };
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+ };
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+ };
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+ };
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+
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+ cluster1 {
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+ cluster0 {
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+ core0 {
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+ thread0 {
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+ cpu = <&CPU8>;
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+ };
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+ thread1 {
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+ cpu = <&CPU9>;
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+ };
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+ };
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+ core1 {
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+ thread0 {
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+ cpu = <&CPU10>;
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+ };
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+ thread1 {
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+ cpu = <&CPU11>;
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+ };
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+ };
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+ };
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+
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+ cluster1 {
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+ core0 {
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+ thread0 {
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+ cpu = <&CPU12>;
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+ };
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+ thread1 {
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+ cpu = <&CPU13>;
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+ };
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+ };
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+ core1 {
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+ thread0 {
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+ cpu = <&CPU14>;
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+ };
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+ thread1 {
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+ cpu = <&CPU15>;
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+ };
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+ };
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+ };
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+ };
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+ };
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+
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+ CPU0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x0>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x1>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU2: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x100>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU3: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x101>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU4: cpu@10000 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x10000>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU5: cpu@10001 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x10001>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU6: cpu@10100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x10100>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU7: cpu@10101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x0 0x10101>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU8: cpu@100000000 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x0>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU9: cpu@100000001 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x1>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU10: cpu@100000100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x100>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU11: cpu@100000101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x101>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU12: cpu@100010000 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x10000>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU13: cpu@100010001 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x10001>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU14: cpu@100010100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x10100>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+
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+ CPU15: cpu@100010101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a57";
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+ reg = <0x1 0x10101>;
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+ enable-method = "spin-table";
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+ cpu-release-addr = <0 0x20000000>;
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+ };
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+};
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+
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+Example 2 (ARM 32-bit, dual-cluster, 8-cpu system, no SMT):
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+
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+cpus {
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+ #size-cells = <0>;
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+ #address-cells = <1>;
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+
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+ cpu-map {
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+ cluster0 {
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+ core0 {
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+ cpu = <&CPU0>;
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+ };
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+ core1 {
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+ cpu = <&CPU1>;
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+ };
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+ core2 {
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+ cpu = <&CPU2>;
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+ };
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+ core3 {
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+ cpu = <&CPU3>;
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+ };
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+ };
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+
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+ cluster1 {
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+ core0 {
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+ cpu = <&CPU4>;
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+ };
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+ core1 {
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+ cpu = <&CPU5>;
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+ };
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+ core2 {
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+ cpu = <&CPU6>;
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+ };
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+ core3 {
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+ cpu = <&CPU7>;
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+ };
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+ };
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+ };
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+
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+ CPU0: cpu@0 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a15";
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+ reg = <0x0>;
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+ };
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+
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+ CPU1: cpu@1 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a15";
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+ reg = <0x1>;
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+ };
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+
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+ CPU2: cpu@2 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a15";
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+ reg = <0x2>;
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+ };
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+
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+ CPU3: cpu@3 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a15";
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+ reg = <0x3>;
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+ };
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+
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+ CPU4: cpu@100 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x100>;
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+ };
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+
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+ CPU5: cpu@101 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
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+ reg = <0x101>;
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+ };
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+
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+ CPU6: cpu@102 {
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+ device_type = "cpu";
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+ compatible = "arm,cortex-a7";
|
|
|
+ reg = <0x102>;
|
|
|
+ };
|
|
|
+
|
|
|
+ CPU7: cpu@103 {
|
|
|
+ device_type = "cpu";
|
|
|
+ compatible = "arm,cortex-a7";
|
|
|
+ reg = <0x103>;
|
|
|
+ };
|
|
|
+};
|
|
|
+
|
|
|
+===============================================================================
|
|
|
+[1] ARM Linux kernel documentation
|
|
|
+ Documentation/devicetree/bindings/arm/cpus.txt
|