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@@ -109,15 +109,18 @@ enum mb5_header {
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#define PRCMU_DSI_CLOCK_SETTING 0x00000128
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/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
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#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
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-#define PRCMU_PLLDSI_FREQ_SETTING 0x0004013C
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+#define PRCMU_PLLDSI_FREQ_SETTING 0x00020121
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#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
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-#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000101
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+#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000201
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#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
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#define PRCMU_ENABLE_PLLDSI 0x00000001
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#define PRCMU_DISABLE_PLLDSI 0x00000000
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#define PRCMU_DSI_RESET_SW 0x00000003
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+#define PRCMU_RESOUTN0_PIN 0x00000001
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+#define PRCMU_RESOUTN1_PIN 0x00000002
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+#define PRCMU_RESOUTN2_PIN 0x00000004
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#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
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