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@@ -34,9 +34,11 @@
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#define REG_SER_CONTROL 24 /*Serial Interface Control Register*/
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#define REG_ID 31 /*ID Register*/
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-/*From figure 17 in the datasheet
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-* These bits get ORed with the address to form
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-* the instruction byte */
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+/*
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+ * From figure 17 in the datasheet
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+ * These bits get ORed with the address to form
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+ * the instruction byte
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+ */
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/*Instruction Bit masks*/
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#define INST_MODE_bm (1<<7)
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#define INST_READ_bm (1<<6)
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@@ -105,8 +107,10 @@ static ssize_t show_voltage(struct device *dev,
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uint8_t channel, mux_cnv;
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channel = attr->index;
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- /*TODO: add support for conversions
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- *other than single ended with a gain of 1*/
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+ /*
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+ * TODO: add support for conversions
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+ * other than single ended with a gain of 1
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+ */
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/*MUX_M3_bm forces single ended*/
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/*This is also where the gain of the PGA would be set*/
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ads7871_write_reg8(spi, REG_GAIN_MUX,
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@@ -114,8 +118,10 @@ static ssize_t show_voltage(struct device *dev,
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ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
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mux_cnv = ((ret & MUX_CNV_bm)>>MUX_CNV_bv);
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- /*on 400MHz arm9 platform the conversion
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- *is already done when we do this test*/
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+ /*
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+ * on 400MHz arm9 platform the conversion
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+ * is already done when we do this test
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+ */
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while ((i < 2) && mux_cnv) {
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i++;
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ret = ads7871_read_reg8(spi, REG_GAIN_MUX);
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@@ -179,8 +185,10 @@ static int __devinit ads7871_probe(struct spi_device *spi)
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ret = ads7871_read_reg8(spi, REG_OSC_CONTROL);
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dev_dbg(&spi->dev, "REG_OSC_CONTROL write:%x, read:%x\n", val, ret);
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- /*because there is no other error checking on an SPI bus
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- we need to make sure we really have a chip*/
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+ /*
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+ * because there is no other error checking on an SPI bus
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+ * we need to make sure we really have a chip
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+ */
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if (val != ret) {
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err = -ENODEV;
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goto exit;
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