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@@ -1,6 +1,22 @@
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#ifndef _X86_SPINLOCK_H_
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#define _X86_SPINLOCK_H_
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+#include <asm/atomic.h>
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+#include <asm/rwlock.h>
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+#include <asm/page.h>
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+#include <asm/processor.h>
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+
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+/*
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+ * Your basic SMP spinlocks, allowing only a single CPU anywhere
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+ *
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+ * Simple spin lock operations. There are two variants, one clears IRQ's
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+ * on the local processor, one does not.
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+ *
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+ * We make no fairness assumptions. They have a cost.
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+ *
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+ * (the type definitions are in asm/spinlock_types.h)
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+ */
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+
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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@@ -11,9 +27,200 @@
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#endif /* CONFIG_PARAVIRT */
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#ifdef CONFIG_X86_32
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-# include "spinlock_32.h"
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+typedef char _slock_t;
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+# define LOCK_INS_DEC "decb"
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+# define LOCK_INS_XCH "xchgb"
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+# define LOCK_INS_MOV "movb"
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+# define LOCK_INS_CMP "cmpb"
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+# define LOCK_PTR_REG "a"
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#else
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-# include "spinlock_64.h"
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+typedef int _slock_t;
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+# define LOCK_INS_DEC "decl"
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+# define LOCK_INS_XCH "xchgl"
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+# define LOCK_INS_MOV "movl"
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+# define LOCK_INS_CMP "cmpl"
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+# define LOCK_PTR_REG "D"
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+#endif
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+
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+static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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+{
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+ return *(volatile _slock_t *)(&(lock)->slock) <= 0;
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+}
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+
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+static inline void __raw_spin_lock(raw_spinlock_t *lock)
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+{
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+ asm volatile(
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+ "\n1:\t"
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+ LOCK_PREFIX " ; " LOCK_INS_DEC " %0\n\t"
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+ "jns 3f\n"
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+ "2:\t"
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+ "rep;nop\n\t"
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+ LOCK_INS_CMP " $0,%0\n\t"
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+ "jle 2b\n\t"
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+ "jmp 1b\n"
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+ "3:\n\t"
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+ : "+m" (lock->slock) : : "memory");
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+}
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+
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+/*
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+ * It is easier for the lock validator if interrupts are not re-enabled
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+ * in the middle of a lock-acquire. This is a performance feature anyway
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+ * so we turn it off:
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+ *
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+ * NOTE: there's an irqs-on section here, which normally would have to be
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+ * irq-traced, but on CONFIG_TRACE_IRQFLAGS we never use this variant.
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+ */
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+#ifndef CONFIG_PROVE_LOCKING
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+static inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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+ unsigned long flags)
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+{
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+ asm volatile(
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+ "\n1:\t"
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+ LOCK_PREFIX " ; " LOCK_INS_DEC " %[slock]\n\t"
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+ "jns 5f\n"
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+ "testl $0x200, %[flags]\n\t"
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+ "jz 4f\n\t"
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+ STI_STRING "\n"
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+ "3:\t"
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+ "rep;nop\n\t"
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+ LOCK_INS_CMP " $0, %[slock]\n\t"
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+ "jle 3b\n\t"
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+ CLI_STRING "\n\t"
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+ "jmp 1b\n"
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+ "4:\t"
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+ "rep;nop\n\t"
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+ LOCK_INS_CMP " $0, %[slock]\n\t"
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+ "jg 1b\n\t"
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+ "jmp 4b\n"
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+ "5:\n\t"
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+ : [slock] "+m" (lock->slock)
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+ : [flags] "r" ((u32)flags)
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+ CLI_STI_INPUT_ARGS
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+ : "memory" CLI_STI_CLOBBERS);
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+}
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+#endif
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+
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+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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+{
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+ _slock_t oldval;
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+
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+ asm volatile(
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+ LOCK_INS_XCH " %0,%1"
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+ :"=q" (oldval), "+m" (lock->slock)
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+ :"0" (0) : "memory");
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+
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+ return oldval > 0;
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+}
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+
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+/*
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+ * __raw_spin_unlock based on writing $1 to the low byte.
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+ * This method works. Despite all the confusion.
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+ * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
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+ * (PPro errata 66, 92)
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+ */
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+#if defined(X86_64) || \
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+ (!defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE))
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+
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+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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+{
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+ asm volatile(LOCK_INS_MOV " $1,%0" : "=m" (lock->slock) :: "memory");
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+}
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+
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+#else
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+
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+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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+{
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+ unsigned char oldval = 1;
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+
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+ asm volatile("xchgb %b0, %1"
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+ : "=q" (oldval), "+m" (lock->slock)
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+ : "0" (oldval) : "memory");
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+}
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+
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#endif
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+static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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+{
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+ while (__raw_spin_is_locked(lock))
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+ cpu_relax();
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+}
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+
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+/*
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+ * Read-write spinlocks, allowing multiple readers
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+ * but only one writer.
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+ *
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+ * NOTE! it is quite common to have readers in interrupts
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+ * but no interrupt writers. For those circumstances we
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+ * can "mix" irq-safe locks - any writer needs to get a
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+ * irq-safe write-lock, but readers can get non-irqsafe
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+ * read-locks.
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+ *
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+ * On x86, we implement read-write locks as a 32-bit counter
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+ * with the high bit (sign) being the "contended" bit.
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+ */
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+
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+static inline int __raw_read_can_lock(raw_rwlock_t *lock)
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+{
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+ return (int)(lock)->lock > 0;
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+}
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+
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+static inline int __raw_write_can_lock(raw_rwlock_t *lock)
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+{
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+ return (lock)->lock == RW_LOCK_BIAS;
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+}
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+
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+static inline void __raw_read_lock(raw_rwlock_t *rw)
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+{
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+ asm volatile(LOCK_PREFIX " subl $1,(%0)\n\t"
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+ "jns 1f\n"
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+ "call __read_lock_failed\n\t"
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+ "1:\n"
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+ ::LOCK_PTR_REG (rw) : "memory");
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+}
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+
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+static inline void __raw_write_lock(raw_rwlock_t *rw)
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+{
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+ asm volatile(LOCK_PREFIX " subl %1,(%0)\n\t"
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+ "jz 1f\n"
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+ "call __write_lock_failed\n\t"
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+ "1:\n"
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+ ::LOCK_PTR_REG (rw), "i" (RW_LOCK_BIAS) : "memory");
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+}
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+
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+static inline int __raw_read_trylock(raw_rwlock_t *lock)
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+{
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+ atomic_t *count = (atomic_t *)lock;
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+
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+ atomic_dec(count);
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+ if (atomic_read(count) >= 0)
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+ return 1;
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+ atomic_inc(count);
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+ return 0;
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+}
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+
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+static inline int __raw_write_trylock(raw_rwlock_t *lock)
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+{
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+ atomic_t *count = (atomic_t *)lock;
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+
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+ if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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+ return 1;
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+ atomic_add(RW_LOCK_BIAS, count);
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+ return 0;
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+}
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+
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+static inline void __raw_read_unlock(raw_rwlock_t *rw)
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+{
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+ asm volatile(LOCK_PREFIX "incl %0" :"+m" (rw->lock) : : "memory");
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+}
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+
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+static inline void __raw_write_unlock(raw_rwlock_t *rw)
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+{
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+ asm volatile(LOCK_PREFIX "addl %1, %0"
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+ : "+m" (rw->lock) : "i" (RW_LOCK_BIAS) : "memory");
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+}
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+
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+#define _raw_spin_relax(lock) cpu_relax()
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+#define _raw_read_relax(lock) cpu_relax()
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+#define _raw_write_relax(lock) cpu_relax()
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+
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#endif
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Thomas Gleixner