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@@ -5181,6 +5181,15 @@ static void lpt_suspend_hw(struct drm_device *dev)
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}
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}
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+static void gen8_init_clock_gating(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = dev->dev_private;
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+
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+ I915_WRITE(WM3_LP_ILK, 0);
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+ I915_WRITE(WM2_LP_ILK, 0);
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+ I915_WRITE(WM1_LP_ILK, 0);
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+}
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+
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static void haswell_init_clock_gating(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@@ -5833,6 +5842,8 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = NULL;
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}
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dev_priv->display.init_clock_gating = haswell_init_clock_gating;
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+ } else if (INTEL_INFO(dev)->gen == 8) {
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+ dev_priv->display.init_clock_gating = gen8_init_clock_gating;
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} else
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dev_priv->display.update_wm = NULL;
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} else if (IS_VALLEYVIEW(dev)) {
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