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@@ -62,15 +62,14 @@ real_start:
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andi r1, r1, ~2
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mts rmsr, r1
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/*
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- * Here is checking mechanism which check if Microblaze has msr instructions
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- * We load msr and compare it with previous r1 value - if is the same,
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- * msr instructions works if not - cpu don't have them.
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+ * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'
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+ * if the msrclr instruction is not enabled. We use this to detect
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+ * if the opcode is available, by issuing msrclr and then testing the result.
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+ * r8 == 0 - msr instructions are implemented
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+ * r8 != 0 - msr instructions are not implemented
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*/
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- /* r8=0 - I have msr instr, 1 - I don't have them */
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- rsubi r0, r0, 1 /* set the carry bit */
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- msrclr r0, 0x4 /* try to clear it */
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- /* read the carry bit, r8 will be '0' if msrclr exists */
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- addik r8, r0, 0
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+ msrclr r8, 0 /* clear nothing - just read msr for test */
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+ cmpu r8, r8, r1 /* r1 must contain msr reg content */
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/* r7 may point to an FDT, or there may be one linked in.
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if it's in r7, we've got to save it away ASAP.
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