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@@ -121,11 +121,37 @@
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#define CHIP_92C 0x01
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#define CHIP_92C 0x01
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#define CHIP_88C 0x00
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#define CHIP_88C 0x00
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+/* Add vendor information into chip version definition.
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+ * Add UMC B-Cut and RTL8723 chip info definition.
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+ *
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+ * BIT 7 Reserved
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+ * BIT 6 UMC BCut
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+ * BIT 5 Manufacturer(TSMC/UMC)
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+ * BIT 4 TEST/NORMAL
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+ * BIT 3 8723 Version
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+ * BIT 2 8723?
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+ * BIT 1 1T2R?
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+ * BIT 0 88C/92C
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+*/
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+
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enum version_8192c {
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enum version_8192c {
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VERSION_A_CHIP_92C = 0x01,
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VERSION_A_CHIP_92C = 0x01,
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VERSION_A_CHIP_88C = 0x00,
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VERSION_A_CHIP_88C = 0x00,
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VERSION_B_CHIP_92C = 0x11,
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VERSION_B_CHIP_92C = 0x11,
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VERSION_B_CHIP_88C = 0x10,
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VERSION_B_CHIP_88C = 0x10,
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+ VERSION_TEST_CHIP_88C = 0x00,
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+ VERSION_TEST_CHIP_92C = 0x01,
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+ VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
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+ VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
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+ VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
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+ VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
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+ VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
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+ VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
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+ VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
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+ VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
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+ VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
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+ VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
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+ VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
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VERSION_UNKNOWN = 0x88,
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VERSION_UNKNOWN = 0x88,
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};
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};
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@@ -254,4 +280,122 @@ struct h2c_cmd_8192c {
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u8 *p_cmdbuffer;
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u8 *p_cmdbuffer;
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};
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};
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+static inline u8 _rtl92c_get_chnl_group(u8 chnl)
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+{
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+ u8 group = 0;
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+
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+ if (chnl < 3)
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+ group = 0;
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+ else if (chnl < 9)
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+ group = 1;
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+ else
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+ group = 2;
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+
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+ return group;
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+}
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+
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+/* NOTE: reference to rtl8192c_rates struct */
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+static inline int _rtl92c_rate_mapping(struct ieee80211_hw *hw, bool isHT,
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+ u8 desc_rate, bool first_ampdu)
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+{
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+ struct rtl_priv *rtlpriv = rtl_priv(hw);
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+ int rate_idx = 0;
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+
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+ if (first_ampdu) {
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+ if (false == isHT) {
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+ switch (desc_rate) {
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+ case DESC92C_RATE1M:
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+ rate_idx = 0;
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+ break;
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+ case DESC92C_RATE2M:
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+ rate_idx = 1;
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+ break;
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+ case DESC92C_RATE5_5M:
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+ rate_idx = 2;
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+ break;
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+ case DESC92C_RATE11M:
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+ rate_idx = 3;
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+ break;
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+ case DESC92C_RATE6M:
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+ rate_idx = 4;
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+ break;
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+ case DESC92C_RATE9M:
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+ rate_idx = 5;
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+ break;
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+ case DESC92C_RATE12M:
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+ rate_idx = 6;
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+ break;
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+ case DESC92C_RATE18M:
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+ rate_idx = 7;
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+ break;
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+ case DESC92C_RATE24M:
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+ rate_idx = 8;
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+ break;
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+ case DESC92C_RATE36M:
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+ rate_idx = 9;
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+ break;
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+ case DESC92C_RATE48M:
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+ rate_idx = 10;
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+ break;
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+ case DESC92C_RATE54M:
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+ rate_idx = 11;
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+ break;
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+ default:
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+ RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
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+ ("Rate %d is not support, set to "
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+ "1M rate.\n", desc_rate));
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+ rate_idx = 0;
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+ break;
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+ }
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+ } else {
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+ rate_idx = 11;
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+ }
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+ return rate_idx;
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+ }
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+ switch (desc_rate) {
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+ case DESC92C_RATE1M:
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+ rate_idx = 0;
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+ break;
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+ case DESC92C_RATE2M:
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+ rate_idx = 1;
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+ break;
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+ case DESC92C_RATE5_5M:
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+ rate_idx = 2;
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+ break;
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+ case DESC92C_RATE11M:
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+ rate_idx = 3;
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+ break;
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+ case DESC92C_RATE6M:
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+ rate_idx = 4;
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+ break;
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+ case DESC92C_RATE9M:
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+ rate_idx = 5;
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+ break;
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+ case DESC92C_RATE12M:
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+ rate_idx = 6;
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+ break;
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+ case DESC92C_RATE18M:
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+ rate_idx = 7;
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+ break;
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+ case DESC92C_RATE24M:
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+ rate_idx = 8;
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+ break;
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+ case DESC92C_RATE36M:
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+ rate_idx = 9;
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+ break;
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+ case DESC92C_RATE48M:
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+ rate_idx = 10;
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+ break;
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+ case DESC92C_RATE54M:
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+ rate_idx = 11;
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+ break;
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+ /* TODO: How to mapping MCS rate? */
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+ /* NOTE: referenc to __ieee80211_rx */
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+ default:
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+ rate_idx = 11;
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+ break;
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+ }
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+ return rate_idx;
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+}
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+
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#endif
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#endif
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