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@@ -1,15 +1,22 @@
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/*
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- * This is based on both include/asm-sh/dma-mapping.h and
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- * include/asm-ppc/pci.h
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+ * Copyright (C) 2004 IBM
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+ *
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+ * Implements the generic device dma API for powerpc.
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+ * the pci and vio busses
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*/
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-#ifndef __ASM_PPC_DMA_MAPPING_H
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-#define __ASM_PPC_DMA_MAPPING_H
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+#ifndef _ASM_DMA_MAPPING_H
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+#define _ASM_DMA_MAPPING_H
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#include <linux/config.h>
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+#include <linux/types.h>
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+#include <linux/cache.h>
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/* need struct page definitions */
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#include <linux/mm.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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+#include <asm/bug.h>
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+
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+#define DMA_ERROR_CODE (~(dma_addr_t)0x0)
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#ifdef CONFIG_NOT_COHERENT_CACHE
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/*
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@@ -24,22 +31,12 @@ extern void __dma_free_coherent(size_t size, void *vaddr);
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extern void __dma_sync(void *vaddr, size_t size, int direction);
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extern void __dma_sync_page(struct page *page, unsigned long offset,
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size_t size, int direction);
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-#define dma_cache_inv(_start,_size) \
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- invalidate_dcache_range(_start, (_start + _size))
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-#define dma_cache_wback(_start,_size) \
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- clean_dcache_range(_start, (_start + _size))
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-#define dma_cache_wback_inv(_start,_size) \
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- flush_dcache_range(_start, (_start + _size))
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#else /* ! CONFIG_NOT_COHERENT_CACHE */
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/*
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* Cache coherent cores.
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*/
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-#define dma_cache_inv(_start,_size) do { } while (0)
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-#define dma_cache_wback(_start,_size) do { } while (0)
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-#define dma_cache_wback_inv(_start,_size) do { } while (0)
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-
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#define __dma_alloc_coherent(gfp, size, handle) NULL
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#define __dma_free_coherent(size, addr) do { } while (0)
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#define __dma_sync(addr, size, rw) do { } while (0)
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@@ -47,6 +44,30 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
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#endif /* ! CONFIG_NOT_COHERENT_CACHE */
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+#ifdef CONFIG_PPC64
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+
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+extern int dma_supported(struct device *dev, u64 mask);
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+extern int dma_set_mask(struct device *dev, u64 dma_mask);
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+extern void *dma_alloc_coherent(struct device *dev, size_t size,
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+ dma_addr_t *dma_handle, gfp_t flag);
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+extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
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+ dma_addr_t dma_handle);
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+extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
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+ size_t size, enum dma_data_direction direction);
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+extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
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+ size_t size, enum dma_data_direction direction);
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+extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
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+ unsigned long offset, size_t size,
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+ enum dma_data_direction direction);
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+extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
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+ size_t size, enum dma_data_direction direction);
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+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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+ enum dma_data_direction direction);
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+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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+ int nhwentries, enum dma_data_direction direction);
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+
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+#else /* CONFIG_PPC64 */
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+
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#define dma_supported(dev, mask) (1)
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static inline int dma_set_mask(struct device *dev, u64 dma_mask)
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@@ -144,29 +165,27 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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/* We don't do anything here. */
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#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
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-static inline void
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-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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- size_t size,
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- enum dma_data_direction direction)
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+#endif /* CONFIG_PPC64 */
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+
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+static inline void dma_sync_single_for_cpu(struct device *dev,
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+ dma_addr_t dma_handle, size_t size,
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+ enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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-
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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-static inline void
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-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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- size_t size,
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- enum dma_data_direction direction)
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+static inline void dma_sync_single_for_device(struct device *dev,
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+ dma_addr_t dma_handle, size_t size,
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+ enum dma_data_direction direction)
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{
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BUG_ON(direction == DMA_NONE);
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-
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__dma_sync(bus_to_virt(dma_handle), size, direction);
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}
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-static inline void
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-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
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- enum dma_data_direction direction)
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+static inline void dma_sync_sg_for_cpu(struct device *dev,
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+ struct scatterlist *sg, int nents,
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+ enum dma_data_direction direction)
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{
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int i;
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@@ -176,9 +195,9 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
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__dma_sync_page(sg->page, sg->offset, sg->length, direction);
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}
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-static inline void
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-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
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- enum dma_data_direction direction)
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+static inline void dma_sync_sg_for_device(struct device *dev,
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+ struct scatterlist *sg, int nents,
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+ enum dma_data_direction direction)
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{
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int i;
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@@ -188,6 +207,15 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
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__dma_sync_page(sg->page, sg->offset, sg->length, direction);
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}
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+static inline int dma_mapping_error(dma_addr_t dma_addr)
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+{
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+#ifdef CONFIG_PPC64
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+ return (dma_addr == DMA_ERROR_CODE);
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+#else
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+ return 0;
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+#endif
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+}
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+
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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#ifdef CONFIG_NOT_COHERENT_CACHE
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@@ -198,40 +226,60 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
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static inline int dma_get_cache_alignment(void)
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{
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+#ifdef CONFIG_PPC64
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+ /* no easy way to get cache size on all processors, so return
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+ * the maximum possible, to be safe */
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+ return (1 << L1_CACHE_SHIFT_MAX);
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+#else
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/*
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* Each processor family will define its own L1_CACHE_SHIFT,
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* L1_CACHE_BYTES wraps to this, so this is always safe.
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*/
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return L1_CACHE_BYTES;
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+#endif
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}
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-static inline void
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-dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
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- unsigned long offset, size_t size,
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- enum dma_data_direction direction)
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+static inline void dma_sync_single_range_for_cpu(struct device *dev,
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+ dma_addr_t dma_handle, unsigned long offset, size_t size,
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+ enum dma_data_direction direction)
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{
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/* just sync everything for now */
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dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
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}
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-static inline void
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-dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
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- unsigned long offset, size_t size,
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- enum dma_data_direction direction)
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+static inline void dma_sync_single_range_for_device(struct device *dev,
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+ dma_addr_t dma_handle, unsigned long offset, size_t size,
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+ enum dma_data_direction direction)
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{
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/* just sync everything for now */
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dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
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}
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static inline void dma_cache_sync(void *vaddr, size_t size,
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- enum dma_data_direction direction)
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+ enum dma_data_direction direction)
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{
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+ BUG_ON(direction == DMA_NONE);
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__dma_sync(vaddr, size, (int)direction);
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}
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-static inline int dma_mapping_error(dma_addr_t dma_addr)
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-{
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- return 0;
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-}
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-
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-#endif /* __ASM_PPC_DMA_MAPPING_H */
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+/*
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+ * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
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+ */
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+struct dma_mapping_ops {
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+ void * (*alloc_coherent)(struct device *dev, size_t size,
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+ dma_addr_t *dma_handle, gfp_t flag);
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+ void (*free_coherent)(struct device *dev, size_t size,
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+ void *vaddr, dma_addr_t dma_handle);
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+ dma_addr_t (*map_single)(struct device *dev, void *ptr,
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+ size_t size, enum dma_data_direction direction);
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+ void (*unmap_single)(struct device *dev, dma_addr_t dma_addr,
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+ size_t size, enum dma_data_direction direction);
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+ int (*map_sg)(struct device *dev, struct scatterlist *sg,
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+ int nents, enum dma_data_direction direction);
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+ void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
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+ int nents, enum dma_data_direction direction);
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+ int (*dma_supported)(struct device *dev, u64 mask);
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+ int (*dac_dma_supported)(struct device *dev, u64 mask);
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+};
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+
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+#endif /* _ASM_DMA_MAPPING_H */
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